To include a phase-difference-amount detecting circuit that detects an amount of phase difference between an external clock signal and a replica clock signal, a variable delay circuit that delays the external clock signal based on the amount of phase difference to generate an internal clock signal, and a replica buffer that delays the internal clock signal to generate the replica clock signal. According to the present invention, the variable delay circuit is controlled based on the amount of phase difference, instead of being controlled based on whether the phase of the replica clock signal is advanced or delayed with respect to the external clock signal. Accordingly, even when the amount of phase difference is large, a DLL circuit can be locked at a high speed.