- 专利标题: Test line placement to improve die sawing quality
-
申请号: US11525575申请日: 2006-09-22
-
公开(公告)号: US08519512B2公开(公告)日: 2013-08-27
- 发明人: Hao-Yi Tsai , Chia-Lun Tsai , Shang-Yun Hou , Shin-Puu Jeng , Shih-Hsun Hsu , Wei-Ti Hsu , Lin-Ko Feng , Chun-Jen Chen
- 申请人: Hao-Yi Tsai , Chia-Lun Tsai , Shang-Yun Hou , Shin-Puu Jeng , Shih-Hsun Hsu , Wei-Ti Hsu , Lin-Ko Feng , Chun-Jen Chen
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Slater & Matsil, L.L.P.
- 主分类号: H01L23/544
- IPC分类号: H01L23/544
摘要:
A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.
公开/授权文献
- US20080073753A1 Test line placement to improve die sawing quality 公开/授权日:2008-03-27
信息查询
IPC分类: