发明授权
- 专利标题: Semiconductor constructions
- 专利标题(中): 半导体结构
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申请号: US13418113申请日: 2012-03-12
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公开(公告)号: US08519516B1公开(公告)日: 2013-08-27
- 发明人: Jaspreet S. Gandhi
- 申请人: Jaspreet S. Gandhi
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 代理机构: Wells St. John P.S.
- 主分类号: H01L23/498
- IPC分类号: H01L23/498 ; H01L21/768
摘要:
Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.
公开/授权文献
- US20130234319A1 SEMICONDUCTOR CONSTRUCTIONS 公开/授权日:2013-09-12
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