Invention Grant
- Patent Title: Hardware acceleration for a software transactional memory system
- Patent Title (中): 软件交易内存系统的硬件加速
-
Application No.: US12782518Application Date: 2010-05-18
-
Publication No.: US08521965B2Publication Date: 2013-08-27
- Inventor: Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn Jacobson
- Applicant: Bratin Saha , Ali-Reza Adl-Tabatabai , Quinn Jacobson
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Barnes & Thornburg LLP
- Main IPC: G06F12/10
- IPC: G06F12/10

Abstract:
A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardware support, such as a transaction field/transaction bits, are provided to determine if an access is the first access to a shared memory line during a pendancy of a transaction. Additionally, in an aggressive operational mode version numbers representing versions of elements stored in shared memory lines are not stored and validated upon commitment to save on validation costs. Moreover, even in a cautious mode, that stores version numbers to enable validation, validation costs may not be incurred, if eviction of accessed shared memory lines do not occur during execution of the transaction.
Public/Granted literature
- US20100229043A1 HARDWARE ACCELERATION FOR A SOFTWARE TRANSACTIONAL MEMORY SYSTEM Public/Granted day:2010-09-09
Information query