Invention Grant
US08531219B1 Phase locked loop with digital compensation for analog integration
有权
具有数字补偿的锁相环,用于模拟集成
- Patent Title: Phase locked loop with digital compensation for analog integration
- Patent Title (中): 具有数字补偿的锁相环,用于模拟集成
-
Application No.: US13866871Application Date: 2013-04-19
-
Publication No.: US08531219B1Publication Date: 2013-09-10
- Inventor: Jeremy D. Dunworth , Gary J. Ballantyne , Bhushan S. Asuri , Jifeng Geng , Gurkanwal S. Sahota
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Kenyon S. Jenckes
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.
Public/Granted literature
- US20130229212A1 PHASE LOCKED LOOP WITH DIGITAL COMPENSATION FOR ANALOG INTEGRATION Public/Granted day:2013-09-05
Information query