发明授权
- 专利标题: Non-volatile memory cell and logic transistor integration
- 专利标题(中): 非易失性存储单元和逻辑晶体管集成
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申请号: US13402426申请日: 2012-02-22
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公开(公告)号: US08536007B2公开(公告)日: 2013-09-17
- 发明人: Mark D. Hall , Mehul D. Shroff
- 申请人: Mark D. Hall , Mehul D. Shroff
- 申请人地址: US TX Austin
- 专利权人: Freescale Semiconductor, Inc.
- 当前专利权人: Freescale Semiconductor, Inc.
- 当前专利权人地址: US TX Austin
- 代理商 James L. Clingan, Jr.; Joanna G. Chiu
- 主分类号: H01L21/8246
- IPC分类号: H01L21/8246
摘要:
A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer is formed over the control gate. A sacrificial layer is formed over the first dielectric layer and planarized. A patterned masking layer is formed over the sacrificial layer which includes a first portion which defines a select gate location laterally adjacent the control gate in the NVM region and a second portion which defines a logic gate in a logic region. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location. A gate dielectric layer and a select gate are formed in the opening.