Invention Grant
US08542513B2 Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
有权
非易失性交叉点存储单元的垂直堆叠层的阵列,形成垂直堆叠层的非易失性交叉点存储单元的阵列的方法,以及读取由非易失性的垂直堆叠层阵列存储的数据值的方法 交叉点存储单元
- Patent Title: Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
- Patent Title (中): 非易失性交叉点存储单元的垂直堆叠层的阵列,形成垂直堆叠层的非易失性交叉点存储单元的阵列的方法,以及读取由非易失性的垂直堆叠层阵列存储的数据值的方法 交叉点存储单元
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Application No.: US13777083Application Date: 2013-02-26
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Publication No.: US08542513B2Publication Date: 2013-09-24
- Inventor: Sanh D. Tang , Gurtej S. Sandhu
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John, P.S.
- Main IPC: G11C5/02
- IPC: G11C5/02 ; G11C5/06 ; G11C11/00 ; H01L21/82

Abstract:
An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.
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