Invention Grant
US08549341B2 System and method for reducing latency associated with timestamps in a multi-core, multi-threaded processor
有权
用于减少与多核,多线程处理器中的时间戳相关联的延迟的系统和方法
- Patent Title: System and method for reducing latency associated with timestamps in a multi-core, multi-threaded processor
- Patent Title (中): 用于减少与多核,多线程处理器中的时间戳相关联的延迟的系统和方法
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Application No.: US12201689Application Date: 2008-08-29
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Publication No.: US08549341B2Publication Date: 2013-10-01
- Inventor: Ahmed Shahid , Kaushik Kuila , David T. Hass
- Applicant: Ahmed Shahid , Kaushik Kuila , David T. Hass
- Applicant Address: US CA Irvine
- Assignee: NetLogic Microsystems, Inc.
- Current Assignee: NetLogic Microsystems, Inc.
- Current Assignee Address: US CA Irvine
- Agency: Sterne, Kessler, Goldstein & Fox PLLC
- Main IPC: G06F1/00
- IPC: G06F1/00

Abstract:
A system and method are provided for reducing a latency associated with timestamps in a multi-core, multi threaded processor. A processor capable of simultaneously processing a plurality of threads is provided. The processor includes a plurality of cores, a plurality of network interfaces for network communication, and a timer circuit for reducing a latency associated with timestamps used for synchronization of the network communication utilizing a precision time protocol.
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