Invention Grant
US08549341B2 System and method for reducing latency associated with timestamps in a multi-core, multi-threaded processor 有权
用于减少与多核,多线程处理器中的时间戳相关联的延迟的系统和方法

System and method for reducing latency associated with timestamps in a multi-core, multi-threaded processor
Abstract:
A system and method are provided for reducing a latency associated with timestamps in a multi-core, multi threaded processor. A processor capable of simultaneously processing a plurality of threads is provided. The processor includes a plurality of cores, a plurality of network interfaces for network communication, and a timer circuit for reducing a latency associated with timestamps used for synchronization of the network communication utilizing a precision time protocol.
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