- 专利标题： Unified optimistic and pessimistic concurrency control for a software transactional memory (STM) system
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申请号： US12337507申请日： 2008-12-17
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公开(公告)号： US08555016B2公开(公告)日： 2013-10-08
- 发明人: Ali-Reza Adl-Tabatabai , Moshe Bach , Sion Berkowits , James Henry Cownie , Yang Ni , Jeffrey V. Olivier , Bratin Saha , Ady Tal , Adam Wele
- 申请人： Ali-Reza Adl-Tabatabai , Moshe Bach , Sion Berkowits , James Henry Cownie , Yang Ni , Jeffrey V. Olivier , Bratin Saha , Ady Tal , Adam Wele
- 申请人地址： US CA santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA santa Clara
- 代理机构： Barnes & Thornburg LLP
- 主分类号： G06F12/00
- IPC分类号： G06F12/00
摘要：
A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.
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