Invention Grant
- Patent Title: Methods of making compliant semiconductor chip packages
- Patent Title (中): 制造兼容半导体芯片封装的方法
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Application No.: US12587714Application Date: 2009-10-13
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Publication No.: US08558386B2Publication Date: 2013-10-15
- Inventor: Joseph Fjelstad , Konstantine Karavakis
- Applicant: Joseph Fjelstad , Konstantine Karavakis
- Applicant Address: US CA San Jose
- Assignee: Tessera, Inc.
- Current Assignee: Tessera, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L29/40
- IPC: H01L29/40

Abstract:
A method of making a semiconductor chip package is provided in which a compliant layer is provided over a contact bearing face of a semiconductor chip. The compliant layer can have a bottom surface adjacent to the chip face, a top surface facing away from the bottom surface, and at least one sloping surface between the top and bottom surfaces. The compliant layer can be disposed remote in a lateral direction along the contact bearing face from at least one contact adjacent to the sloping surface. Bond ribbons can be formed atop the compliant layer, wherein each bond ribbon electrically connects one of the contacts to an associated conductive terminal at the top surface of the compliant layer. The compliant layer can provide stress relief to the bond ribbons, such as during handling and affixing the assembly to an external substrate. A bond ribbon can include a strip extending along the sloping surface of the compliant layer, the strip having a substantially constant thickness in a direction extending away from the sloping surface.
Public/Granted literature
- US20100035382A1 Methods of making compliant semiconductor chip packages Public/Granted day:2010-02-11
Information query
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