发明授权
US08563391B2 Method for forming MIM capacitor in a copper damascene interconnect
有权
在铜镶嵌互连中形成MIM电容器的方法
- 专利标题: Method for forming MIM capacitor in a copper damascene interconnect
- 专利标题(中): 在铜镶嵌互连中形成MIM电容器的方法
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申请号: US12316956申请日: 2008-12-17
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公开(公告)号: US08563391B2公开(公告)日: 2013-10-22
- 发明人: Chun-Hong Chen , Minghsing Tsai
- 申请人: Chun-Hong Chen , Minghsing Tsai
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Duane Morris LLP
- 主分类号: H01L21/20
- IPC分类号: H01L21/20
摘要:
A method for forming a metal-insulator-metal capacitor in a multilevel semiconductor device utilizes the copper interconnect levels of the semiconductor device as parts of the capacitor. A lower capacitor plate consists of a copper interconnect level and a first metal layer formed on the copper interconnect level by selective deposition methods. The upper capacitor plate includes the same pattern as the capacitor dielectric, the pattern having an area less than the area of the lower capacitor plate. The upper capacitor plate is formed of a second metal layer. The first and second metal layers may each be formed of cobalt, tungsten, nickel, molybdenum, or a combinations of one of the aforementioned elements with boron and/or phosphorus. Conductive vias provide contact from the upper capacitor plate and lower capacitor plate, to interconnect levels.