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    MIM capacitor in a copper damascene interconnect
    1.
    发明授权
    MIM capacitor in a copper damascene interconnect 有权
    MIM电容器在铜镶嵌互连中

    公开(公告)号：US07483258B2

    公开(公告)日：2009-01-27

    申请号：US11300567

    申请日：2005-12-13

    申请人： Chun-Hong Chen ,  Minghsing Tsai

    发明人： Chun-Hong Chen ,  Minghsing Tsai

    IPC分类号： H01G4/38

    CPC分类号： H01L23/5223 ,  H01L23/53228 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal-insulator-metal capacitor formed in a multilevel semiconductor device utilizes the copper interconnect levels of the semiconductor device as parts of the capacitor. A lower capacitor plate consists of a copper interconnect level and a first metal layer formed on the copper interconnect level by selective deposition methods. The upper capacitor plate includes the same pattern as the capacitor dielectric, the pattern having an area less than the area of the lower capacitor plate. The upper capacitor plate is formed of a second metal layer. The first and second metal layers may each be formed of cobalt, tungsten, nickel, molybdenum, or a combinations of one of the aforementioned elements with boron and/or phosphorus. Conductive vias provide contact from the upper capacitor plate and lower capacitor plate, to interconnect levels.

    摘要翻译： 形成在多电平半导体器件中的金属 - 绝缘体 - 金属电容器利用半导体器件的铜互连电平作为电容器的部分。 下电容器板由铜互连层和通过选择性沉积方法形成在铜互连层上的第一金属层组成。 上部电容器板包括与电容器电介质相同的图案，该图案具有小于下部电容器板的面积的面积。 上部电容器板由第二金属层形成。 第一和第二金属层可以各自由钴，钨，镍，钼或上述元素之一与硼和/或磷的组合形成。 导电通孔提供从上电容器板和下电容器板到互连电平的接触。

    Method for forming MIM capacitor in a copper damascene interconnect
    2.
    发明授权
    Method for forming MIM capacitor in a copper damascene interconnect 有权
    在铜镶嵌互连中形成MIM电容器的方法

    公开(公告)号：US08563391B2

    公开(公告)日：2013-10-22

    申请号：US12316956

    申请日：2008-12-17

    申请人： Chun-Hong Chen ,  Minghsing Tsai

    发明人： Chun-Hong Chen ,  Minghsing Tsai

    IPC分类号： H01L21/20

    CPC分类号： H01L23/5223 ,  H01L23/53228 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming a metal-insulator-metal capacitor in a multilevel semiconductor device utilizes the copper interconnect levels of the semiconductor device as parts of the capacitor. A lower capacitor plate consists of a copper interconnect level and a first metal layer formed on the copper interconnect level by selective deposition methods. The upper capacitor plate includes the same pattern as the capacitor dielectric, the pattern having an area less than the area of the lower capacitor plate. The upper capacitor plate is formed of a second metal layer. The first and second metal layers may each be formed of cobalt, tungsten, nickel, molybdenum, or a combinations of one of the aforementioned elements with boron and/or phosphorus. Conductive vias provide contact from the upper capacitor plate and lower capacitor plate, to interconnect levels.

    摘要翻译： 在多电平半导体器件中形成金属 - 绝缘体 - 金属电容器的方法利用半导体器件的铜互连电平作为电容器的一部分。 下电容器板由铜互连层和通过选择性沉积方法形成在铜互连层上的第一金属层组成。 上部电容器板包括与电容器电介质相同的图案，该图案具有小于下部电容器板的面积的面积。 上部电容器板由第二金属层形成。 第一和第二金属层可以各自由钴，钨，镍，钼或上述元素之一与硼和/或磷的组合形成。 导电通孔提供从上电容器板和下电容器板到互连电平的接触。

    Method for forming min capacitor in a copper damascene interconnect
    3.
    发明申请
    Method for forming min capacitor in a copper damascene interconnect 有权
    在铜镶嵌互连中形成最小电容器的方法

    公开(公告)号：US20090111234A1

    公开(公告)日：2009-04-30

    申请号：US12316956

    申请日：2008-12-17

    申请人： Chun-Hong Chen ,  Minghsing Tsai

    发明人： Chun-Hong Chen ,  Minghsing Tsai

    IPC分类号： H01L21/20

    CPC分类号： H01L23/5223 ,  H01L23/53228 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming a metal-insulator-metal capacitor in a multilevel semiconductor device utilizes the copper interconnect levels of the semiconductor device as parts of the capacitor. A lower capacitor plate consists of a copper interconnect level and a first metal layer formed on the copper interconnect level by selective deposition methods. The upper capacitor plate includes the same pattern as the capacitor dielectric, the pattern having an area less than the area of the lower capacitor plate. The upper capacitor plate is formed of a second metal layer. The first and second metal layers may each be formed of cobalt, tungsten, nickel, molybdenum, or a combinations of one of the aforementioned elements with boron and/or phosphorus. Conductive vias provide contact from the upper capacitor plate and lower capacitor plate, to interconnect levels.

    摘要翻译： 在多电平半导体器件中形成金属 - 绝缘体 - 金属电容器的方法利用半导体器件的铜互连电平作为电容器的一部分。 下电容器板由铜互连层和通过选择性沉积方法形成在铜互连层上的第一金属层组成。 上部电容器板包括与电容器电介质相同的图案，该图案具有小于下部电容器板的面积的面积。 上部电容器板由第二金属层形成。 第一和第二金属层可以各自由钴，钨，镍，钼或上述元素之一与硼和/或磷的组合形成。 导电通孔提供从上电容器板和下电容器板到互连电平的接触。

    MIM capacitor in a copper damascene interconnect
    4.
    发明申请
    MIM capacitor in a copper damascene interconnect 有权
    MIM电容器在铜镶嵌互连中

    公开(公告)号：US20070132061A1

    公开(公告)日：2007-06-14

    申请号：US11300567

    申请日：2005-12-13

    申请人： Chun-Hong Chen ,  Minghsing Tsai

    发明人： Chun-Hong Chen ,  Minghsing Tsai

    IPC分类号： H01L29/00 ,  H01L21/00

    CPC分类号： H01L23/5223 ,  H01L23/53228 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal-insulator-metal capacitor formed in a multilevel semiconductor device utilizes the copper interconnect levels of the semiconductor device as parts of the capacitor. A lower capacitor plate consists of a copper interconnect level and a first metal layer formed on the copper interconnect level by selective deposition methods. The upper capacitor plate includes the same pattern as the capacitor dielectric, the pattern having an area less than the area of the lower capacitor plate. The upper capacitor plate is formed of a second metal layer. The first and second metal layers may each be formed of cobalt, tungsten, nickel, molybdenum, or a combinations of one of the aforementioned elements with boron and/or phosphorus. Conductive vias provide contact from the upper capacitor plate and lower capacitor plate, to interconnect levels.

    摘要翻译： 形成在多电平半导体器件中的金属 - 绝缘体 - 金属电容器利用半导体器件的铜互连电平作为电容器的部分。 下电容器板由铜互连层和通过选择性沉积方法形成在铜互连层上的第一金属层组成。 上部电容器板包括与电容器电介质相同的图案，该图案具有小于下部电容器板的面积的面积。 上部电容器板由第二金属层形成。 第一和第二金属层可以各自由钴，钨，镍，钼或上述元素之一与硼和/或磷的组合形成。 导电通孔提供从上电容器板和下电容器板到互连电平的接触。

    Dummy shoulder structure for line stress reduction
    5.
    发明授权
    Dummy shoulder structure for line stress reduction 有权
    用于线应力降低的假肩结构

    公开(公告)号：US08692351B2

    公开(公告)日：2014-04-08

    申请号：US12753272

    申请日：2010-04-02

    申请人： Cheng Cheng Kuo ,  Luke Lo ,  Minghsing Tsai ,  Ken-Yu Chang ,  Jye-Yen Cheng ,  Jeng-Shiun Ho ,  Hua-Tai Lin ,  Chih-Hsiang Yao

    发明人： Cheng Cheng Kuo ,  Luke Lo ,  Minghsing Tsai ,  Ken-Yu Chang ,  Jye-Yen Cheng ,  Jeng-Shiun Ho ,  Hua-Tai Lin ,  Chih-Hsiang Yao

    IPC分类号： H01L21/70

    CPC分类号： H01L21/76838 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.

    摘要翻译： 在本公开中描述了用于改善密集到隔离图案转移区域附近的处理窗口的半导体集成电路线结构和在布局处理中实现线结构的技术。 所公开的结构包括半导体衬底和衬底上方的材料层。 材料层具有紧密间隔的密集线结构，紧密密集线结构旁边的隔离线结构，以及形成在密集线附近和隔离线结构处的虚拟线肩结构。 虚拟线肩结构的一端连接到隔离线结构，另一端以基本垂直于隔离线结构的方向远离隔离线结构延伸。

    Metal structure with sidewall passivation and method
    8.
    发明申请
    Metal structure with sidewall passivation and method 有权
    金属结构与侧壁钝化和方法

    公开(公告)号：US20060189143A1

    公开(公告)日：2006-08-24

    申请号：US11061350

    申请日：2005-02-18

    申请人： Minghsing Tsai ,  Yung-Cheng Lu

    发明人： Minghsing Tsai ,  Yung-Cheng Lu

    IPC分类号： H01L21/311

    CPC分类号： H01L21/76834 ,  H01L21/02118 ,  H01L21/0226 ,  H01L21/3127 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76835

    摘要： A passivated metal structure and a method of forming the metal structure is disclosed. According to one embodiment, the patterned metal structure, such as conductive lines, are formed on a substrate. The copper lines are passivated by a polymer liner between the copper lines and a low k dielectric filling the spaces between the conductive lines. The polymer liner is preferably deposited on the sidewalls of the conductive lines by electro-grafting. The polymer liner may also be used in a damascene process according to a second embodiment.

    摘要翻译： 公开了钝化金属结构和形成金属结构的方法。 根据一个实施例，图案化的金属结构，例如导电线，形成在基板上。 铜线由铜线之间的聚合物衬垫和填充导电线之间的空间的低k电介质钝化。 聚合物衬垫优选通过电接枝沉积在导电线的侧壁上。 聚合物衬垫也可以用于根据第二实施例的镶嵌工艺中。

    Passivation structure for semiconductor devices
    9.
    发明申请
    Passivation structure for semiconductor devices 审中-公开
    半导体器件钝化结构

    公开(公告)号：US20060138668A1

    公开(公告)日：2006-06-29

    申请号：US11023296

    申请日：2004-12-27

    申请人： Hung-Wen Su ,  Chien-Hsueh Shih ,  Minghsing Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

    发明人： Hung-Wen Su ,  Chien-Hsueh Shih ,  Minghsing Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC分类号： H01L23/06

    CPC分类号： H01L23/53238 ,  H01L21/288 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76865 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system and method for providing a passivation structure for semiconductor devices is provided. In an embodiment, the passivation structure comprises a first barrier layer and a second barrier layer, wherein the second barrier layer may comprise a material, such as cobalt and/or nickel, that is less pure than the first barrier layer. In another embodiment, a single gradient barrier layer is formed. In this embodiment the single gradient barrier layer exhibits a greater pure conductive material, such as cobalt and/or nickel, nearer the conductive line than near the surface.

    摘要翻译： 提供了一种用于提供半导体器件的钝化结构的系统和方法。 在一个实施例中，钝化结构包括第一阻挡层和第二阻挡层，其中第二阻挡层可以包括比第一阻挡层更纯的材料，例如钴和/或镍。 在另一个实施例中，形成单个梯度阻挡层。 在该实施例中，单个梯度阻挡层表现出比在表面附近更靠近导电线的较高纯度的导电材料，例如钴和/或镍。

    Approach for reducing copper line resistivity
    10.
    发明授权
    Approach for reducing copper line resistivity 有权
    降低铜线电阻率的方法

    公开(公告)号：US08242016B2

    公开(公告)日：2012-08-14

    申请号：US11803282

    申请日：2007-05-14

    申请人： Hsien-Ming Lee ,  Minghsing Tsai ,  Syun-Ming Jang

    发明人： Hsien-Ming Lee ,  Minghsing Tsai ,  Syun-Ming Jang

    IPC分类号： H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/76856 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873

    摘要： A method for fabricating an integrated circuit structure and the resulting integrated circuit structure are provided. The method includes forming a low-k dielectric layer; form an opening in the low-k dielectric layer; forming a barrier layer covering a bottom and sidewalls of the low-k dielectric layer; performing a treatment to the barrier layer in an environment comprising a treatment gas; and filling the opening with a conductive material, wherein the conductive material is on the barrier layer.

    摘要翻译： 提供一种用于制造集成电路结构的方法和所得到的集成电路结构。 该方法包括形成低k电介质层; 在低k电介质层中形成开口; 形成覆盖所述低k电介质层的底部和侧壁的阻挡层; 在包括处理气体的环境中对阻挡层进行处理; 并用导电材料填充开口，其中导电材料在阻挡层上。