Invention Grant
US08564067B2 Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure
有权
配置为减少谐波的绝缘体上硅(SOI)结构和形成结构的方法
- Patent Title: Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure
- Patent Title (中): 配置为减少谐波的绝缘体上硅(SOI)结构和形成结构的方法
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Application No.: US13772402Application Date: 2013-02-21
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Publication No.: US08564067B2Publication Date: 2013-10-22
- Inventor: Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Gibb & Riley, LLC
- Agent Anthony J. Canale
- Main IPC: H01L21/70
- IPC: H01L21/70

Abstract:
Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.
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