Invention Grant
US08564348B1 Clock generator for generating output clock having non-harmonic relationship with input clock and related clock generating method thereof
有权
时钟发生器，用于产生与输入时钟非谐波关系的输出时钟及其相关的时钟产生方法
- Patent Title: Clock generator for generating output clock having non-harmonic relationship with input clock and related clock generating method thereof
- Patent Title (中): 时钟发生器，用于产生与输入时钟非谐波关系的输出时钟及其相关的时钟产生方法
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Application No.: US13925858Application Date: 2013-06-25
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Publication No.: US08564348B1Publication Date: 2013-10-22
- Inventor: Robert Bogdan Staszewski , Chi-Hsueh Wang
- Applicant: Mediatek Inc.
- Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
- Assignee: Mediatek Inc.
- Current Assignee: Mediatek Inc.
- Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: H03L7/06
- IPC: H03L7/06
Abstract:
A clock generator has an oscillator block and an output block. The oscillator block provides a second clock of multiple phases, and includes an oscillator and a delay locked loop (DLL). The oscillator is used to provide a first clock. The DLL is used to generate the second clock according to the first clock. The output block is used to receive the second clock and generate a third clock by selecting signals from the multiple phases, wherein the third clock has non-harmonic relationship the first clock.
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