Invention Grant
- Patent Title: Blocking layers for leakage current reduction in DRAM devices
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Application No.: US13658065Application Date: 2012-10-23
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Publication No.: US08569818B2Publication Date: 2013-10-29
- Inventor: Sandra G. Malhotra , Hanhong Chen , Wim Y. Deweerd , Hiroyuki Ode
- Applicant: Intermolecular, Inc.
- Applicant Address: US CA San Jose
- Assignee: Intermolecular, Inc.
- Current Assignee: Intermolecular, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H01L29/94
- IPC: H01L29/94 ; H01L21/20
Abstract:
A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.
Public/Granted literature
- US20130113079A1 Blocking Layers for Leakage Current Reduction in DRAM Devices Public/Granted day:2013-05-09
Information query
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