公开(公告)号：US20150087130A1

公开(公告)日：2015-03-26

申请号：US14033326

申请日：2013-09-20

申请人： Elpida Memory, Inc ,  Intermolecular, Inc.

发明人： Hanhong Chen ,  David Chi ,  Imran Hashim ,  Mitsuhiro Horikawa ,  Sandra G. Malhotra

IPC分类号： H01L49/02

CPC分类号： H01L28/56 ,  H01L27/108 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/75 ,  H01L28/82

摘要： A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.

摘要翻译： 形成电容器堆叠的方法包括形成包括导电金属氮化物材料的第一底部电极层。 在第一底部电极层的上方形成第二底部电极层。 第二底部电极层包括导电金属氧化物材料，其中导电金属氧化物材料的晶体结构促进随后沉积的介电层的期望的高k结晶相。 在第二底部电极层的上方形成电介质层。 任选地，在介电层上方形成富氧金属氧化物层。 可选地，在富氧金属氧化物层的上方形成第三上电极层。 第三顶部电极层包括导电金属氧化物材料。 第四上电极层形成在第三顶电极层的上方。 第四顶部电极层包括导电金属氮化物材料。

公开(公告)号：US08737036B2

公开(公告)日：2014-05-27

申请号：US13657782

申请日：2012-10-22

申请人： Intermolecular, Inc.

发明人： Hanhong Chen ,  Nobumichi Fuchigami ,  Imran Hashim ,  Edward L. Haywood ,  Pragati Kumar ,  Sandra G. Malhotra ,  Monica Sawkar Mathur ,  Prashant B. Phatak ,  Sunil Shanker

IPC分类号： H01G4/30

CPC分类号： H01G4/1218 ,  C23C16/405 ,  C23C16/45531 ,  C23C16/56 ,  H01G4/33 ,  H01L21/02186 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02312 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/3142 ,  H01L28/40

摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle. The process provides high deposition rates, and the resulting MIM structure has substantially no x-ray diffraction peaks associated with anatase-phase titanium oxide.

摘要翻译： 本公开内容提供（a）制造基于氧化钛的氧化物层（例如电介质层）的方法，以抑制锐钛矿相氧化钛的形成和（b）相关的器件和结构。 使用底部电极（或其他基底）的臭氧预处理随后进行ALD工艺来形成金属 - 绝缘体 - 金属（“MIM”）堆叠，以形成根植于使用含酰胺的前体的TiO 2电介质。 在ALD工艺之后，氧化退火工艺的应用热度足以愈合TiO2电介质中的缺陷，并降低TiO2和电极之间的界面态; 选择退火温度以使其不那么热，以致破坏BEL表面粗糙度。 进一步的工艺变型可以包括在ALD工艺期间掺杂氧化钛，基座加热至275-300摄氏度，对于BEL使用铂或钌，对于每个ALD工艺循环使用多个试剂脉冲的臭氧。 该方法提供高沉积速率，并且所得MIM结构基本上没有与锐钛矿相氧化钛相关的x射线衍射峰。

公开(公告)号：US20140077336A1

公开(公告)日：2014-03-20

申请号：US13737125

申请日：2013-01-09

申请人： INTERMOLECULAR INC.

发明人： Tony P. Chiang ,  Wim Y. Deweerd ,  Sandra G. Malhotra

IPC分类号： H01L29/92

CPC分类号： H01L29/92 ,  H01L27/10852 ,  H01L28/40

摘要： A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

摘要翻译： 用于形成具有低漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 在电介质层上形成无定形阻挡层。 选择阻挡层的厚度使得在随后的退火处理之后阻挡层保持无定形。 在阻挡层上形成与阻挡层相容的第二电极层。

公开(公告)号：US20140042384A1

公开(公告)日：2014-02-13

申请号：US14058518

申请日：2013-10-21

申请人： Intermolecular Inc.

发明人： Pragati Kumar ,  Sean Barstow ,  Tony P. Chiang ,  Sandra G. Malhotra

IPC分类号： H01L45/00

CPC分类号： H01L45/1253 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/861 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/165

摘要： Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.

摘要翻译： 包括电阻开关金属氧化物的非易失性存储元件可以形成在集成电路上的一个或多个层中。 每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。 诸如二极管的电气设备可以与存储器元件串联耦合。 第一导电层可以由金属氮化物形成。 金属氧化物层可以包含与第一导电层相同的金属。 金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。 第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。 第一导电层，金属氧化物层和第二导电层可以包括子层。 第二导电层可以包括粘合或阻挡层和功函数控制层。

公开(公告)号：US08633039B2

公开(公告)日：2014-01-21

申请号：US13932640

申请日：2013-07-01

申请人： Intermolecular, Inc.

发明人： Gaurav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G. Malhotra ,  Prashant B. Phatak ,  Kurt H. Weiner

IPC分类号： H01L21/00

CPC分类号： G01R31/2831 ,  G01R31/2834 ,  H01L22/34

摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

摘要翻译： 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

公开(公告)号：US20130328168A1

公开(公告)日：2013-12-12

申请号：US13737467

申请日：2013-01-09

申请人： INTERMOLECULAR INC.

发明人： Sandra G. Malhotra ,  Wim Y. Deweerd ,  Hiroyuki Ode

IPC分类号： H01L49/02

CPC分类号： H01L28/56 ,  H01L27/10852 ,  H01L28/60 ,  H01L28/90

摘要： A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin ( 3nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material.

摘要翻译： 描述形成电容器堆叠的方法。 在本发明的一些实施例中，第一电介质材料形成在第一电极材料之上。 第一电极材料是刚性的并且具有良好的机械强度并且用作用于电容器叠层的坚固框架。 第一介电材料足够薄（<2nm）或高度掺杂，使得在随后的退火处理之后它保持非晶态。 在第一电介质材料上方形成第二电介质材料。 第二介电材料足够厚（> 3nm）或轻掺杂或未掺杂，使得其在随后的退火处理之后结晶。 与第二电介质材料相邻地形成第二电极材料。 第二电极材料具有高功函数和用于促进形成第二电介质材料的高k值晶体结构的晶体结构。

公开(公告)号：US08581318B1

公开(公告)日：2013-11-12

申请号：US13737209

申请日：2013-01-09

申请人： Intermolecular, Inc.

发明人： Hanhong Chen ,  Wim Deweerd ,  Edward L. Haywood ,  Sandra G. Malhotra ,  Hiroyuki Ode

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L28/60 ,  H01L28/75

摘要： A metal oxide first electrode material for a MIM DRAM capacitor is formed wherein the first and/or second electrode materials or structures contain layers having one or more dopants up to a total doping concentration that will not prevent the electrode materials from crystallizing during a subsequent anneal step. Advantageously, the electrode doped with one or more of the dopants has a work function greater than about 5.0 eV. Advantageously, the electrode doped with one or more of the dopants has a resistivity less than about 1000 μΩcm. Advantageously, the electrode materials are conductive molybdenum oxide.

摘要翻译： 形成用于MIM DRAM电容器的金属氧化物第一电极材料，其中第一和/或第二电极材料或结构包含具有一个或多个掺杂剂的层，直到总掺杂浓度，其将不会阻止电极材料在随后的退火期间结晶 步。 有利地，掺杂有一种或多种掺杂剂的电极具有大于约5.0eV的功函数。 有利地，掺杂有一种或多种掺杂剂的电极具有小于约1000微米的电阻率。 有利地，电极材料是导电性氧化钼。

公开(公告)号：US20130217202A1

公开(公告)日：2013-08-22

申请号：US13830282

申请日：2013-03-14

申请人： Intermolecular, Inc. ,  Elpida Memory, Inc.

发明人： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi ,  Hiroyuki Ode ,  Xiangxin Rui

IPC分类号： H01L49/02

CPC分类号： H01L28/60 ,  H01L28/40 ,  H01L28/75

摘要： A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

公开(公告)号：US20130217200A1

公开(公告)日：2013-08-22

申请号：US13829378

申请日：2013-03-14

申请人： Intermolecular Inc.

发明人： Pragati KUMAR ,  Sean Barstow ,  Tony P. Chiang ,  Sandra G. Malhotra

IPC分类号： H01L45/00

CPC分类号： H01L45/1253 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/861 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/165

摘要： Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.

摘要翻译： 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以形成在集成电路上的一个或多个层中。 每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。 诸如二极管的电气设备可以与存储器元件串联耦合。 第一导电层可以由金属氮化物形成。 金属氧化物层可以包含与第一导电层相同的金属。 金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。 第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。 第一导电层，金属氧化物层和第二导电层可以包括子层。 第二导电层可以包括粘合或阻挡层和功函数控制层。

公开(公告)号：US09281357B2

公开(公告)日：2016-03-08

申请号：US14599843

申请日：2015-01-19

申请人： Intermolecular, Inc. ,  Elpida Memory, Inc

发明人： Hanhong Chen ,  David Chi ,  Imran Hashim ,  Mitsuhiro Horikawa ,  Sandra G. Malhotra

IPC分类号： H01L49/02 ,  H01L27/108

CPC分类号： H01L28/56 ,  H01L27/108 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/75 ,  H01L28/82

摘要： A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.