Invention Grant
- Patent Title: Bipolar transistor integrated with metal gate CMOS devices
- Patent Title (中): 与金属栅极CMOS器件集成的双极晶体管
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Application No.: US13370523Application Date: 2012-02-10
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Publication No.: US08569840B2Publication Date: 2013-10-29
- Inventor: Thomas A. Wallner , Ebenezer E. Eshun , Daniel J. Jaeger , Phung T. Nguyen
- Applicant: Thomas A. Wallner , Ebenezer E. Eshun , Daniel J. Jaeger , Phung T. Nguyen
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent H. Daniel Schnurmann
- Main IPC: H01L29/70
- IPC: H01L29/70 ; H01L29/73 ; H01L29/78
Abstract:
A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.
Public/Granted literature
- US20120139056A1 BIPOLAR TRANSISTOR INTEGRATED WITH METAL GATE CMOS DEVICES Public/Granted day:2012-06-07
Information query
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