Invention Grant
- Patent Title: Stacked dual chip package and method of fabrication
- Patent Title (中): 堆叠式双芯片封装及其制造方法
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Application No.: US12819111Application Date: 2010-06-18
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Publication No.: US08581376B2Publication Date: 2013-11-12
- Inventor: Hamza Yilmaz , Xiaotian Zhang , Yan Xun Xue , Anup Bhalla , Jun Lu , Kai Liu , Yueh-Se Ho , John Amato
- Applicant: Hamza Yilmaz , Xiaotian Zhang , Yan Xun Xue , Anup Bhalla , Jun Lu , Kai Liu , Yueh-Se Ho , John Amato
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha & Omega Semiconductor Incorporated
- Current Assignee: Alpha & Omega Semiconductor Incorporated
- Current Assignee Address: US CA Sunnyvale
- Agent Kenneth C. Brooks
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/31
Abstract:
The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.
Public/Granted literature
- US20110227207A1 STACKED DUAL CHIP PACKAGE AND METHOD OF FABRICATION Public/Granted day:2011-09-22
Information query
IPC分类:
