Invention Grant
- Patent Title: Integrated circuit packaging system with ultra-thin die
- Patent Title (中): 集成电路封装系统采用超薄型芯片
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Application No.: US11456554Application Date: 2006-07-10
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Publication No.: US08581380B2Publication Date: 2013-11-12
- Inventor: Soo-San Park , Sang-Ho Lee , Jong-Woo Ha
- Applicant: Soo-San Park , Sang-Ho Lee , Jong-Woo Ha
- Applicant Address: SG Singapore
- Assignee: Stats Chippac Ltd.
- Current Assignee: Stats Chippac Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Agent I-Chang John Yang
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
An integrated circuit packaging system with ultra-thin die is provided including providing an ultra-thin integrated circuit stack, having a vertical sidewall contact, including providing a semiconductor wafer having an active side, forming a solder bump on the active side of the semiconductor wafer, forming a support layer over the solder bump and the active side of the semiconductor wafer, forming an ultra-thin wafer from the semiconductor wafer and singulating the ultra-thin integrated circuit stack for exposing the vertical sidewall contact, mounting the ultra-thin integrated circuit stack on a substrate, and coupling the substrate to the vertical sidewall contact.
Public/Granted literature
- US20080006921A1 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ULTRA-THIN DIE Public/Granted day:2008-01-10
Information query
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