Invention Grant
- Patent Title: Gate height loss improvement for a transistor
- Patent Title (中): 晶体管的栅极高度损耗改善
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Application No.: US13335771Application Date: 2011-12-22
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Publication No.: US08598028B2Publication Date: 2013-12-03
- Inventor: Che-Hao Tu , Chi-Jen Liu , Tzu-Chung Wang , Weilun Hong , Ying-Tsung Chen , Liang-Guang Chen
- Applicant: Che-Hao Tu , Chi-Jen Liu , Tzu-Chung Wang , Weilun Hong , Ying-Tsung Chen , Liang-Guang Chen
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L21/20

Abstract:
The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure over an iso region of a substrate and a second gate structure over a dense region of the substrate. The dense region has a greater pattern density than the iso region. The first and second gate structures each have a respective hard mask disposed thereon. The method includes removing the hard masks from the first and second gate structures. The removal of the hard mask from the second gate structure causes an opening to be formed in the second gate structure. The method includes performing a deposition process followed by a first polishing process to form a sacrificial component in the opening. The method includes performing a second polishing process to remove the sacrificial component and portions of the first and second gate structures.
Public/Granted literature
- US20130164930A1 GATE HEIGHT LOSS IMPROVEMENT FOR A TRANSISTOR Public/Granted day:2013-06-27
Information query
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