发明授权
US08600049B2 Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation
有权
用于在并行运行模式下优化先进加密标准（AES）加密和解密的方法和装置
- 专利标题： Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation
- 专利标题（中）： 用于在并行运行模式下优化先进加密标准（AES）加密和解密的方法和装置
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申请号： US13506701申请日： 2012-05-10
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公开(公告)号： US08600049B2公开(公告)日： 2013-12-03
- 发明人: Shay Gueron , Amit Gradstein , Zeev Sperber
- 申请人： Shay Gueron , Amit Gradstein , Zeev Sperber
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理商 L. Cho
- 主分类号： H04L9/00
- IPC分类号： H04L9/00
摘要：
The throughput of an encryption/decryption operation is increased in a system having a pipelined execution unit. Different independent encryptions (decryptions) of different data blocks may be performed in parallel by dispatching an AES round instruction in every cycle.
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