Invention Grant
- Patent Title: Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic
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Application No.: US13175500Application Date: 2011-07-01
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Publication No.: US08607129B2Publication Date: 2013-12-10
- Inventor: Sivakumar Radhakrishnan , Mark A. Schmisseur , Sin S. Tan , Kenneth C. Haren , Thomas C. Brown , Pankaj Kumar , Vinodh Gopal , Wajdi K. Feghali
- Applicant: Sivakumar Radhakrishnan , Mark A. Schmisseur , Sin S. Tan , Kenneth C. Haren , Thomas C. Brown , Pankaj Kumar , Vinodh Gopal , Wajdi K. Feghali
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H03M13/00
- IPC: H03M13/00 ; G06F11/10
Abstract:
Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.
Public/Granted literature
- US20130007573A1 EFFICIENT AND SCALABLE CYCLIC REDUNDANCY CHECK CIRCUIT USING GALOIS-FIELD ARITHMETIC Public/Granted day:2013-01-03
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