Invention Grant
- Patent Title: Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith
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Application No.: US13869112Application Date: 2013-04-24
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Publication No.: US08609488B2Publication Date: 2013-12-17
- Inventor: Jaydip Guha , Shyam Surthi , Suraj J. Mathew , Kamal M. Karda , Hung-Ming Tsai
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John, P.S.
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L21/336
Abstract:
Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.
Public/Granted literature
- US20130237023A1 Methods Of Forming A Vertical Transistor And At Least A Conductive Line Electrically Coupled Therewith Public/Granted day:2013-09-12
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