发明授权
- 专利标题: Integrated circuit including a buried wiring line
- 专利标题(中): 集成电路包括埋地布线
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申请号: US12135318申请日: 2008-06-09
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公开(公告)号: US08618600B2公开(公告)日: 2013-12-31
- 发明人: Stafan Slesazeck
- 申请人: Stafan Slesazeck
- 申请人地址: DE Munich
- 专利权人: Qimonda AG
- 当前专利权人: Qimonda AG
- 当前专利权人地址: DE Munich
- 代理机构: Dicke, Billig & Czaja, PLLC
- 主分类号: H01L29/66
- IPC分类号: H01L29/66
摘要:
Integrated circuits including a buried wiring lien. One embodiment provides a field effect transistor including a first active area and a gate electrode buried below a main surface of a semiconductor substrate. A gate wiring line may be buried below the main surface and a section of the gate wiring line may form the gate electrode. Above the gate wiring line, a buried contact structure is formed that is adjacent to and in direct contact with the first or a second active area.
公开/授权文献
- US20090302392A1 INTEGRATED CIRCUIT INCLUDING A BURIED WIRING LINE 公开/授权日:2009-12-10