Invention Grant
- Patent Title: Failsafe galvanic isolation barrier
- Patent Title (中): 故障电流隔离屏障
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Application No.: US13197136Application Date: 2011-08-03
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Publication No.: US08625242B2Publication Date: 2014-01-07
- Inventor: Roberto Alini , Rajesh Kumar Gupta , Baris Posat
- Applicant: Roberto Alini , Rajesh Kumar Gupta , Baris Posat
- Applicant Address: US CA San Jose
- Assignee: Maxim Integrated Products, Inc.
- Current Assignee: Maxim Integrated Products, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H02H3/20
- IPC: H02H3/20

Abstract:
A system includes a transmitter, a receiver, a isolation barrier, and a fuse. The isolation barrier is connected to the transmitter. The fuse is connected between the isolation barrier and the receiver. The isolation barrier prevents current flow from the transmitter to the receiver when a voltage across the isolation barrier is less than a first breakdown voltage. The isolation barrier short circuits when the voltage across the isolation barrier is greater than or equal to the first breakdown voltage. The fuse opens when the isolation barrier short circuits. When open, the fuse has a second breakdown voltage that is greater than the first breakdown voltage.
Public/Granted literature
- US20130033791A1 FAILSAFE GALVANIC ISOLATION BARRIER Public/Granted day:2013-02-07
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