发明授权
US08626480B2 Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors
失效
紧凑型器件/电路/芯片泄漏电流(IDDQ)计算,包括工艺引起的隆起因素
- 专利标题: Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors
- 专利标题(中): 紧凑型器件/电路/芯片泄漏电流(IDDQ)计算,包括工艺引起的隆起因素
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申请号: US12574440申请日: 2009-10-06
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公开(公告)号: US08626480B2公开(公告)日: 2014-01-07
- 发明人: Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jae-Eun Park , Kern Rim , Xiaojun Yu
- 申请人: Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jae-Eun Park , Kern Rim , Xiaojun Yu
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Scully, Scott, Murphy & Presser, P.C.
- 代理商 Joseph P. Abate, Esq.
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.