公开(公告)号：US08626480B2

公开(公告)日：2014-01-07

申请号：US12574440

申请日：2009-10-06

申请人： Paul Chang ,  Jie Deng ,  Terrence B. Hook ,  Sim Y. Loo ,  Anda C. Mocuta ,  Jae-Eun Park ,  Kern Rim ,  Xiaojun Yu

发明人： Paul Chang ,  Jie Deng ,  Terrence B. Hook ,  Sim Y. Loo ,  Anda C. Mocuta ,  Jae-Eun Park ,  Kern Rim ,  Xiaojun Yu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G01R31/2848 ,  G01R31/3008 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5036

摘要： A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.

摘要翻译： 一种用于将静态电流泄漏特定模型实现为半导体器件设计和电路设计流程的系统，方法和计算机程序产品。 泄漏模型涵盖宽温度和电压范围的所有器件几何，并且不需要堆叠因子计算，也不需要基于平板的IDDQ计算。 IDDQ计算的泄漏模型包含进一步的寄生和邻近效应。 泄漏模型在不同的测试水平下实施泄漏计算，例如从单个设备到全芯片设计，并且集成在一个单一的模型中。 泄漏模型通过单个开关设置的杠杆来实现不同测试级别的泄漏计算。 该实现是通过硬件定义语言代码或面向对象的代码，其可以使用感兴趣的网表来编译和操作，例如用于进行性能分析。

公开(公告)号：US20110082680A1

公开(公告)日：2011-04-07

申请号：US12574440

申请日：2009-10-06

申请人： Paul Chang ,  Jie Deng ,  Terrence B. Hook ,  Sim Y. Loo ,  Anda C. Mocuta ,  Jae-Eun Park ,  Kern Rim ,  Xiaojun Yu

发明人： Paul Chang ,  Jie Deng ,  Terrence B. Hook ,  Sim Y. Loo ,  Anda C. Mocuta ,  Jae-Eun Park ,  Kern Rim ,  Xiaojun Yu

IPC分类号： G06F17/50 ,  G06F17/18 ,  G01R31/26

CPC分类号： G06F17/5081 ,  G01R31/2848 ,  G01R31/3008 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5036

摘要： A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.

摘要翻译： 一种用于将静态电流泄漏特定模型实现为半导体器件设计和电路设计流程的系统，方法和计算机程序产品。 泄漏模型涵盖宽温度和电压范围的所有器件几何，并且不需要堆叠因子计算，也不需要基于平板的IDDQ计算。 IDDQ计算的泄漏模型包含进一步的寄生和邻近效应。 泄漏模型在不同的测试水平下实施泄漏计算，例如从单个设备到全芯片设计，并且集成在一个单一的模型中。 泄漏模型通过单个开关设置的杠杆来实现不同测试级别的泄漏计算。 该实现是通过硬件定义语言代码或面向对象的代码，其可以使用感兴趣的网表来编译和操作，例如用于进行性能分析。

公开(公告)号：US20130168673A1

公开(公告)日：2013-07-04

申请号：US13342226

申请日：2012-01-03

申请人： Xiaojun Yu ,  Anda C. Mocuta ,  Toshiaki Kirihata

发明人： Xiaojun Yu ,  Anda C. Mocuta ,  Toshiaki Kirihata

IPC分类号： H01L23/58 ,  H01L21/66

CPC分类号： H01L22/34 ,  H01L23/481 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： An apparatus comprising connecting IDVMON monitors with through silicon vias (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of the wafer have significantly more space than the front side, the probe pads for IDVMON can be accommodated without sacrificing the silicon area.

摘要翻译： 一种设备，包括通过硅通孔（TSV）连接IDVMON监视器，以使监视器能够连接到位于晶片背面的探针焊盘。 因为晶片的背面具有比前侧大得多的空间，所以可以容纳用于IDVMON的探针垫，而不牺牲硅面积。

公开(公告)号：US08754412B2

公开(公告)日：2014-06-17

申请号：US13342226

申请日：2012-01-03

申请人： Xiaojun Yu ,  Anda C. Mocuta ,  Toshiaki Kirihata

发明人： Xiaojun Yu ,  Anda C. Mocuta ,  Toshiaki Kirihata

IPC分类号： H01L29/10

CPC分类号： H01L22/34 ,  H01L23/481 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： An apparatus comprising connecting IDVMON monitors with through silicon vias (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of the wafer have significantly more space than the front side, the probe pads for IDVMON can be accommodated without sacrificing the silicon area.

摘要翻译： 一种设备，包括通过硅通孔（TSV）连接IDVMON监视器，以使监视器能够连接到位于晶片背面的探针焊盘。 因为晶片的背面具有比前侧大得多的空间，所以可以容纳用于IDVMON的探针垫，而不牺牲硅面积。

公开(公告)号：US20130168776A1

公开(公告)日：2013-07-04

申请号：US13342435

申请日：2012-01-03

申请人： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

发明人： Yue Liang ,  Dureseti Chidambarrao ,  Brian J. Greene ,  William K. Henson ,  Unoh Kwon ,  Shreesh Narasimha ,  Xiaojun Yu

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823871 ,  H01L21/28079 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/4958

摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.

摘要翻译： 一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。 连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。 与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

公开(公告)号：US20130126976A1

公开(公告)日：2013-05-23

申请号：US13298783

申请日：2011-11-17

申请人： Xiaojun Yu ,  Dureseti Chidambarrao ,  Brian J. Greene ,  Yue Liang

发明人： Xiaojun Yu ,  Dureseti Chidambarrao ,  Brian J. Greene ,  Yue Liang

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823871 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/092

摘要： A complementary metal oxide semiconductor (CMOS) device that may include a substrate having a first active region and a second active region that are separated from one another by an isolation region. An n-type semiconductor device is present on the first active region that includes a first gate structure having a first gate dielectric layer and an n-type work function metal layer, wherein the n-type work function layer does not extend onto the isolation region. A p-type semiconductor device is present on the second active region that includes a second gate structure having a second gate dielectric layer and a p-type work function metal layer, wherein the p-type work function layer does not extend onto the isolation region. A connecting gate structure extends across the isolation region into direct contact with the first gate structure and the second gate structure.

摘要翻译： 互补金属氧化物半导体（CMOS）器件，其可以包括具有通过隔离区彼此分离的第一有源区和第二有源区的衬底。 在第一有源区上存在n型半导体器件，其包括具有第一栅极介电层和n型功函数金属层的第一栅极结构，其中n型功函数层不延伸到隔离区 。 p型半导体器件存在于第二有源区，其包括具有第二栅极介电层和p型功函数金属层的第二栅极结构，其中p型功函数层不延伸到隔离区 。 连接栅极结构跨越隔离区域延伸成与第一栅极结构和第二栅极结构直接接触。

公开(公告)号：US08445974B2

公开(公告)日：2013-05-21

申请号：US12683602

申请日：2010-01-07

申请人： Dureseti Chidambarrao ,  Sunfei Fang ,  Yue Liang ,  Xiaojun Yu ,  Jun Yuan

发明人： Dureseti Chidambarrao ,  Sunfei Fang ,  Yue Liang ,  Xiaojun Yu ,  Jun Yuan

IPC分类号： H01L21/02

CPC分类号： H01L27/092 ,  H01L21/823857 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/78

摘要： A semiconductor structure is provided that includes at least one asymmetric gate stack located on a surface of a semiconductor structure. The at least one asymmetric gate stack includes, from bottom to top, a high k gate dielectric, a sloped threshold voltage adjusting material layer and a gate conductor. A method of forming such a semiconductor structure is also provided in which a line of sight deposition process is used in forming the sloped threshold voltage adjusting material layer in which the deposition is tilted within respect to a horizontal surface of a semiconductor structure.

摘要翻译： 提供一种半导体结构，其包括位于半导体结构的表面上的至少一个非对称栅极堆叠。 所述至少一个非对称栅极堆叠包括从底部到顶部的高k栅极电介质，倾斜阈值电压调节材料层和栅极导体。 还提供了一种形成这种半导体结构的方法，其中在形成相对于半导体结构的水平表面倾斜的沉积倾斜的阈值电压调节材料层中使用视线沉积工艺。

公开(公告)号：US20120108017A1

公开(公告)日：2012-05-03

申请号：US13347014

申请日：2012-01-10

申请人： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

发明人： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

IPC分类号： H01L21/782 ,  H01L21/8238

CPC分类号： H01L21/823462 ,  H01L21/28229 ,  H01L21/84 ,  H01L27/1203

摘要： Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

摘要翻译： 在掺杂半导体阱上形成多种类型的栅叠层。 在掺杂半导体阱上形成高介电常数（高k）栅极电介质。 在一个器件区域中形成金属栅极层，而在其他器件区域中暴露高k栅极电介质。 在其他器件区域中形成具有不同厚度的阈值电压调节氧化物层。 然后在阈值电压调整氧化物层上形成导电栅极材料层。 一种类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质。 其他类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质和具有不同厚度的第一阈值电压调整氧化物部分。 具有不同阈值电压的场效应晶体管通过采用具有相同掺杂剂浓度的不同栅极电介质叠层和掺杂半导体阱来提供。

公开(公告)号：US20100032732A1

公开(公告)日：2010-02-11

申请号：US12187003

申请日：2008-08-06

申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei ,  Ravi M. Todi ,  Xiaojun Yu

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei ,  Ravi M. Todi ,  Xiaojun Yu

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L23/525

CPC分类号： H01L23/5252 ,  H01L27/11206 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical antifuse comprising a field effect transistor includes a gate dielectric having two gate dielectric portions. Upon application of electric field across the gate dielectric, the magnitude of the electrical field is locally enhanced at the boundary between the thick and thin gate dielectric portions due to the geometry, thereby allowing programming of the electrical antifuse at a lower supply voltage between the two electrodes, i.e., the body and the gate electrode of the transistor, across the gate dielectric.

摘要翻译： 包括场效应晶体管的电反熔丝包括具有两个栅电介质部分的栅极电介质。 在栅极电介质上施加电场时，由于几何形状，在厚和薄栅介质部分之间的边界处，电场的幅度被局部增强，从而允许在两个电源电压之间的较低电源电压下对电反熔丝进行编程 电极，即晶体管的主体和栅电极，跨过栅极电介质。

公开(公告)号：US08853035B2

公开(公告)日：2014-10-07

申请号：US13253375

申请日：2011-10-05

申请人： Xiaojun Yu ,  Brian J. Greene ,  Yue Liang

发明人： Xiaojun Yu ,  Brian J. Greene ,  Yue Liang

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L21/28

CPC分类号： H01L29/7848 ,  H01L21/02112 ,  H01L21/02532 ,  H01L21/28123 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66568 ,  H01L29/66636

摘要： In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.

摘要翻译： 在一个实施例中，提供了半导体器件，其包括半导体衬底，该半导体衬底包括有源区和位于有源区的周边的至少一个沟槽隔离区，以及存在于半导体衬底的有源区的一部分上的功能栅结构 。 嵌入式半导体区域存在于半导体衬底的有源区域中，在有源区域的存在功能栅极结构的部分的相对侧上。 半导体衬底的有源区域的一部分将嵌入的半导体区域的最外边缘与至少一个隔离区域分开。 还提供了形成上述装置的方法。