发明授权
US08633094B2 GaN high voltage HFET with passivation plus gate dielectric multilayer structure
失效
GaN高电压HFET具有钝化加栅极电介质多层结构
- 专利标题： GaN high voltage HFET with passivation plus gate dielectric multilayer structure
- 专利标题（中）： GaN高电压HFET具有钝化加栅极电介质多层结构
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申请号： US13373811申请日： 2011-12-01
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公开(公告)号： US08633094B2公开(公告)日： 2014-01-21
- 发明人: Jamal Ramdani , Linlin Liu , John Paul Edwards
- 申请人： Jamal Ramdani , Linlin Liu , John Paul Edwards
- 申请人地址： US CA San Jose
- 专利权人： Power Integrations, Inc.
- 当前专利权人： Power Integrations, Inc.
- 当前专利权人地址： US CA San Jose
- 代理机构： The Law Offices of Bradley J. Bereznak
- 主分类号： H01L29/778
- IPC分类号： H01L29/778
摘要：
A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device.
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