发明授权
US08635387B2 Enhanced I/O performance in a multi-processor system via interrupt affinity schemes
有权
通过中断关联方案在多处理器系统中提高I / O性能
- 专利标题: Enhanced I/O performance in a multi-processor system via interrupt affinity schemes
- 专利标题(中): 通过中断关联方案在多处理器系统中提高I / O性能
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申请号: US12577031申请日: 2009-10-09
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公开(公告)号: US08635387B2公开(公告)日: 2014-01-21
- 发明人: Qiang Liu , Allen Russell Andrews , David Bradley Baldwin
- 申请人: Qiang Liu , Allen Russell Andrews , David Bradley Baldwin
- 申请人地址: US CA Costa Mesa
- 专利权人: Emulex Design & Manufacturing Corporation
- 当前专利权人: Emulex Design & Manufacturing Corporation
- 当前专利权人地址: US CA Costa Mesa
- 代理机构: McAndrews, Held & Malloy, Ltd.
- 主分类号: G06F3/00
- IPC分类号: G06F3/00 ; G06F13/24
摘要:
Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.