- 专利标题： Translation of input/output addresses to memory addresses
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申请号： US12821170申请日： 2010-06-23
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公开(公告)号： US08635430B2公开(公告)日： 2014-01-21
- 发明人: David Craddock , Thomas A. Gregg , Dan F. Greiner , Eric N. Lais
- 申请人： David Craddock , Thomas A. Gregg , Dan F. Greiner , Eric N. Lais
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Heslin, Rothenberg, Farley & Mesiti P.C.
- 代理商 John E. Campbell; Blanche E. Schiller, Esq.
- 主分类号： G06F12/00
- IPC分类号： G06F12/00
摘要：
An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.