发明授权
- 专利标题: Capacitor array layout arrangement for high matching methodology
- 专利标题(中): 高匹配方法的电容阵列布局布置
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申请号: US13602471申请日: 2012-09-04
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公开(公告)号: US08643141B2公开(公告)日: 2014-02-04
- 发明人: Chung-Ting Lu , Chih-Chiang Chang
- 申请人: Chung-Ting Lu , Chih-Chiang Chang
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Eschweiler & Associates, LLC
- 主分类号: H01L21/02
- IPC分类号: H01L21/02 ; H01L21/20
摘要:
Some embodiments relate a capacitor array arranged on a semiconductor substrate. The capacitor array includes an array of unit capacitors arranged in a series of rows and columns. An interconnect structure couples unit capacitors of the array to establish a plurality of capacitor elements. The respective capacitor elements have different numbers of unit capacitors and different corresponding capacitances. In establishing the plurality of capacitor elements, the interconnect structure couples unit capacitors of the array in substantially identical sub-arrays tiled over the semiconductor substrate. Other methods and devices are also disclosed.
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