发明授权
- 专利标题: Structure and method for bump to landing trace ratio
- 专利标题(中): 撞击到达轨迹比的结构和方法
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申请号: US13426386申请日: 2012-03-21
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公开(公告)号: US08643196B2公开(公告)日: 2014-02-04
- 发明人: Chen-Hua Yu , Tin-Hao Kuo , Chen-Shien Chen , Mirng-Ji Lii , Sheng-Yu Wu , Yen-Liang Lin
- 申请人: Chen-Hua Yu , Tin-Hao Kuo , Chen-Shien Chen , Mirng-Ji Lii , Sheng-Yu Wu , Yen-Liang Lin
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Haynes and Boone, LLP
- 主分类号: H01L23/48
- IPC分类号: H01L23/48 ; H01L23/52 ; H01L29/40
摘要:
The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T.
公开/授权文献
- US20130026614A1 STRUCTURE AND METHOD FOR BUMP TO LANDING TRACE RATIO 公开/授权日:2013-01-31