利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

23829 条记录 (耗时 0.052 秒)

    Semiconductor Device and Method of Manufacture
    2.
    发明申请
    Semiconductor Device and Method of Manufacture 审中-公开

    公开(公告)号：US20190067179A1

    公开(公告)日：2019-02-28

    申请号：US16108535

    申请日：2018-08-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Hung Jui Chang ,  Li-Te Hsu

    IPC分类号： H01L23/498 ,  H01L21/768

    摘要： A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the porous dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the porous dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230140731A1

    公开(公告)日：2023-05-04

    申请号：US17668392

    申请日：2022-02-10

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Huai-Ying Huang ,  Yu-Ming Lin

    IPC分类号： H01L27/11 ,  G11C11/4091 ,  H01L27/108 ,  G11C11/419 ,  G11C16/26 ,  H01L27/11526 ,  H01L27/11573

    摘要： A semiconductor device includes a semiconductor substrate, ground level circuitry, a plurality of stacked memory arrays and a plurality of sense amplifier units. The ground level circuitry is disposed on the semiconductor substrate. The stacked memory arrays are disposed at an elevated level over the ground level circuitry. The sense amplifier units are disposed on the semiconductor substrate and electrically coupled to the stacked memory arrays, wherein at least a portion of each of the sense amplifier units is disposed at the elevated level over the ground level circuitry.

    FILTER MEMBRANE AND METHOD FOR MAKING THE SAME
    7.
    发明申请
    FILTER MEMBRANE AND METHOD FOR MAKING THE SAME 有权

    公开(公告)号：US20230138216A1

    公开(公告)日：2023-05-04

    申请号：US17682254

    申请日：2022-02-28

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： En-Tian LIN ,  Chwen YU

    IPC分类号： B01D67/00 ,  B01D69/02

    摘要： A method for making a filter membrane includes: forming a polymer layer; applying a plurality of nanoparticles on the polymer layer, the nanoparticles being self-assembled to form a closed pack arrangement on the polymer layer; heating the nanoparticles such that a portion of the polymer layer contacting the nanoparticles is softened so that the nanoparticles are sunk into the polymer layer; and removing the nanoparticles from the polymer layer so that the polymer layer is formed with a plurality of pores penetrating the polymer layer and being arranged in a honeycomb pattern.

    MEMORY DEVICE
    8.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20230134975A1

    公开(公告)日：2023-05-04

    申请号：US17684951

    申请日：2022-03-02

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Tzu-Hsien Yang ,  Chia-En Huang ,  Yih Wang ,  Jonathan Tsung-Yung Chang

    IPC分类号： G11C11/4097 ,  G11C11/4091

    摘要： A memory device is provided. A first sub-block of the memory device includes first memory cells arranged in a first row and connected to a first bit line and second of memory cells arranged in a second row and connected to a first complementary bit line. The first memory cells and the second memory cells are connected to word lines in a first connection pattern. A second sub-block of the memory device includes third memory cells arranged in a third row and connected to a second bit line and fourth memory cells arranged in a fourth row and connected to a complementary second bit line. The third memory cells and the fourth memory cells are connected to the word lines in a second connection pattern that is different from the first connection pattern.

    Semiconductor structure
    10.
    发明授权
    Semiconductor structure 有权

    公开(公告)号：US11640962B2

    公开(公告)日：2023-05-02

    申请号：US17385626

    申请日：2021-07-26

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Jhon-Jhy Liaw

    IPC分类号： H01L27/092 ,  H01L27/11 ,  H01L23/532 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8238 ,  H01L23/522 ,  H01L29/66

    摘要： Semiconductor structures are provided. A first logic cell includes a plurality of first transistors over a substrate. The first transistor includes a first gate electrode across a first channel region. The first gate electrode is electrically connected to a first conductive line in a first dielectric layer through a first contact in a second dielectric layer and a first via in the first dielectric layer. A second logic cell includes a plurality of second transistors over the substrate. The second transistor includes a second gate electrode across a second channel region, wherein the second gate electrode is electrically connected to a second conductive line in the first dielectric layer through a second via. The first dielectric layer is formed over the second dielectric layer, and the second via extends from the second conductive line to the second gate electrode and penetrates the first and second dielectric layers.