Invention Grant
- Patent Title: Method of manufacturing vertical planar power MOSFET and method of manufacturing trench-gate power MOSFET
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Application No.: US13742489Application Date: 2013-01-16
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Publication No.: US08647948B2Publication Date: 2014-02-11
- Inventor: Satoshi Eguchi , Yuya Abiko , Junichi Kogure
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Mattingly & Malur, PC
- Priority: JP2012-013030 20120125
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L21/336

Abstract:
In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.
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