Invention Grant
- Patent Title: FPGA configuration data scrambling using input multiplexers
- Patent Title (中): 使用输入多路复用器的FPGA配置数据加扰
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Application No.: US10942151Application Date: 2004-09-15
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Publication No.: US08650409B1Publication Date: 2014-02-11
- Inventor: Dirk Reese , Thomas H. White
- Applicant: Dirk Reese , Thomas H. White
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Ropes & Gray LLP
- Main IPC: G06F21/00
- IPC: G06F21/00

Abstract:
Circuits, methods, and apparatus that provide for protection of configuration bitstreams from theft. One exemplary embodiment receives a scrambled configuration bitstream with an integrated circuit. The scrambled configuration bitstream is descrambled using a plurality of multiplexers under control of a security key. A configuration bitstream is received in portions. One specific embodiment uses a key stored in memory to control a bank of multiplexers that descramble each of the received portions of the configuration bitstream. Other embodiments store longer keys, and use portions of the keys to descramble one or more portions of their respective configuration bitstreams. The outputs of the multiplexers are then stored in configuration memory cells.
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