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    FPGA configuration data scrambling using input multiplexers
    1.
    发明授权
    FPGA configuration data scrambling using input multiplexers 有权
    使用输入多路复用器的FPGA配置数据加扰

    公开(公告)号：US08650409B1

    公开(公告)日：2014-02-11

    申请号：US10942151

    申请日：2004-09-15

    Applicant: Dirk Reese ,  Thomas H. White

    Inventor： Dirk Reese ,  Thomas H. White

    IPC: G06F21/00

    CPC classification number: H03K19/017581 ,  G06F21/72 ,  G06F21/76 ,  G06F2221/2107 ,  G09C1/00 ,  H04L9/0897

    Abstract: Circuits, methods, and apparatus that provide for protection of configuration bitstreams from theft. One exemplary embodiment receives a scrambled configuration bitstream with an integrated circuit. The scrambled configuration bitstream is descrambled using a plurality of multiplexers under control of a security key. A configuration bitstream is received in portions. One specific embodiment uses a key stored in memory to control a bank of multiplexers that descramble each of the received portions of the configuration bitstream. Other embodiments store longer keys, and use portions of the keys to descramble one or more portions of their respective configuration bitstreams. The outputs of the multiplexers are then stored in configuration memory cells.

    Abstract translation: 提供保护配置比特流免遭盗窃的电路，方法和设备。 一个示例性实施例使用集成电路接收加扰配置比特流。 在安全密钥的控制下，使用多个多路复用器对扰频配置比特流进行解扰。 部分接收配置比特流。 一个具体实施例使用存储在存储器中的密钥来控制解扰配置比特流的每个接收部分的多路复用器组。 其他实施例存储较长的密钥，并且使用密钥的部分来解扰其各自配置比特流的一个或多个部分。 然后将多路复用器的输出存储在配置存储单元中。

    Techniques for configuring programmable logic using on-chip nonvolatile memory
    3.
    发明授权
    Techniques for configuring programmable logic using on-chip nonvolatile memory 有权
    使用片上非易失性存储器配置可编程逻辑的技术

    公开(公告)号：US07375551B1

    公开(公告)日：2008-05-20

    申请号：US11335032

    申请日：2006-01-18

    Applicant: Thomas H. White ,  William Bradley Vest ,  Dirk Alan Reese ,  Myron Wong

    Inventor： Thomas H. White ,  William Bradley Vest ,  Dirk Alan Reese ,  Myron Wong

    IPC: H03K19/173

    CPC classification number: G06F17/5054 ,  H03K19/17764

    Abstract: Techniques and circuitry provide fast, accurate, proper, and reliable transfer of configuration data from an on-chip nonvolatile memory to the programmable logic core of a programmable logic integrated circuit. A first technique includes not allowing the programmable logic to be configured until the data held in the on-chip nonvolatile memory can be read correctly and reliably. A second technique includes verifying the configuration data is transferred from the nonvolatile memory to the programmable logic core correctly and without error during the transfer process. These two techniques may be combined or used individually during the configuration of an integrated circuit.

    Abstract translation: 技术和电路提供从片上非易失性存储器到可编程逻辑集成电路的可编程逻辑核心的快速，准确，适当和可靠的配置数据传输。 第一种技术包括不允许配置可编程逻辑，直到可以正确可靠地读取保持在片上非易失性存储器中的数据。 第二种技术包括验证在传送过程中配置数据是否从非易失性存储器传送到可编程逻辑核心，并且在传送过程中没有错误。 这两种技术可以在集成电路的配置期间单独组合或使用。

    Integrated circuit devices with power supply detection circuitry
    4.
    发明授权
    Integrated circuit devices with power supply detection circuitry 失效

    公开(公告)号：US06985010B2

    公开(公告)日：2006-01-10

    申请号：US10753056

    申请日：2004-01-06

    Applicant: Sergey Y. Shumarayev ,  Thomas H. White

    Inventor： Sergey Y. Shumarayev ,  Thomas H. White

    IPC: H03K19/003

    CPC classification number: H03K17/22 ,  G06F1/24 ,  G06F1/28

    Abstract: Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.

    Operating station for aircraft refueling boom
    7.
    发明授权
    Operating station for aircraft refueling boom 失效
    飞机加油站运行站

    公开(公告)号：US4264044A

    公开(公告)日：1981-04-28

    申请号：US644

    申请日：1979-01-02

    Applicant: Thomas H. White

    Inventor： Thomas H. White

    IPC: B64D39/00

    CPC classification number: B64D39/00

    Abstract: A refueling boom operator's seat located within the lower rear portion of the aircraft fuselage, the seat positioning the operator in a moderately reclining sitting position facing rearwardly to view the operating area of the refueling boom. A leg well structure which extends rearwardly through and beyond a rear pressure bulkhead to accommodate the operator's legs, and a viewing window provided in an aperture defined by the rear pressure bulkhead is positioned above the operator's legs at approximately the position of the operator's knees. These components are so arranged relative to the main rear pressure bulkhead and other components of the fuselage that the operator has a direct unobstructed view of the boom's normal refueling envelope. A pair of mirrors at the upper and lower portion of the viewing window envelope provide a view of the area into which the boom is able to move above its normal refueling area.

    Abstract translation: 位于飞机机身下后部的加油臂操作者座椅，座椅将操作者定位在向后向后的适度倾斜的坐姿中以观察加油臂的操作区域。 一个腿部井结构，其向后延伸穿过后部压力舱壁并且超过后部压力舱壁，以容纳操作者的腿部，并且设置在由后部压力舱壁限定的孔中的观察窗被设置在操作者的腿部的大约在操作者膝盖的位置的上方。 这些部件相对于主后压舱壁和机身的其他部件设置得如此布置，使得操作者能够直接畅通地看到起重臂的正常加油信封。 在观察窗口信封的上部和下部的一对反射镜提供了悬臂能够在其正常加油区域上方移动的区域的视图。

    Memory elements with soft error upset immunity
    8.
    发明授权
    Memory elements with soft error upset immunity 有权
    内存元件具有软错误的不安定性

    公开(公告)号：US08432724B2

    公开(公告)日：2013-04-30

    申请号：US12753809

    申请日：2010-04-02

    Applicant: Thomas H. White

    Inventor： Thomas H. White

    IPC: G11C11/00

    CPC classification number: G11C7/02 ,  G11C11/4125 ,  G11C11/419

    Abstract: Integrated circuits with memory cells are provided. A memory cell may have four inverter-like circuits connected in a ring configuration and four corresponding storage nodes. The four inverter-like circuits may form a storage portion of the memory cell. Some of the inverter-like circuits may have tri-state transistors in pull-up and pull-down paths. The tri-state transistors may be controlled by address signals. Address and access transistors may be coupled between some of the storages nodes and a data line. The address and access transistors may be used to read and write into the memory cell. During write operations, the address signals may be asserted to turn off the tri-state transistors and eliminate contention current from the cell. During read and normal operations, the address signals may be deasserted to allow the inverter-like circuits to hold the current state of the cell while providing soft error upset immunity.

    Abstract translation: 提供具有存储单元的集成电路。 存储单元可以具有以环形配置连接的四个逆变器状电路和四个对应的存储节点。 四个逆变器状电路可以形成存储单元的存储部分。 一些逆变器状电路可以在上拉和下拉路径中具有三态晶体管。 三态晶体管可以由地址信号控制。 地址和存取晶体管可以耦合在一些存储节点和数据线之间。 地址和存取晶体管可用于读写存储单元。 在写操作期间，可以断言地址信号以关闭三态晶体管并消除来自该单元的竞争电流。 在读取和正常操作期间，可以将地址信号置为无效，以允许类似逆变器的电路保持电池的当前状态，同时提供软错误不耐受性。

    Integrated circuit devices with power supply detection circuitry
    10.
    发明授权
    Integrated circuit devices with power supply detection circuitry 有权
    具有电源检测电路的集成电路器件

    公开(公告)号：US07345509B2

    公开(公告)日：2008-03-18

    申请号：US11193006

    申请日：2005-07-29

    Applicant: Sergey Y Shumarayev ,  Thomas H White

    Inventor： Sergey Y Shumarayev ,  Thomas H White

    IPC: H03K19/003

    CPC classification number: H03K17/22 ,  G06F1/24 ,  G06F1/28

    Abstract: Integrated circuit devices are provided that include power detection circuits that indicate whether power supplies have reached functional voltage levels. The power detection circuits include latches coupled to power supplies that can detect whether all the power supplies have reached functional voltage levels, logic circuits to provide appropriate output signals, and well bias circuits that supply current to the power detection circuits. Well bias circuits provide current from first power supplies to reach functional voltage levels so that indication may be provided from the power detection circuit without requiring functional voltage levels of all power supplies. Outputs from power detection circuits can be combined with control signals, for various applications. Applications include holding an integrated circuit device in reset until power supplies have reached functional voltage levels.

    Abstract translation: 提供集成电路装置，其包括指示电源是否达到功能电压电平的功率检测电路。 功率检测电路包括耦合到电源的锁存器，其可以检测所有电源是否已经达到功能电压电平，逻辑电路以提供适当的输出信号，以及向电力检测电路提供电流的阱偏置电路。 良好的偏置电路提供来自第一电源的电流以达到功能电压电平，使得可以从功率检测电路提供指示，而不需要所有电源的功能电压电平。 来自功率检测电路的输出可以与控制信号组合，用于各种应用。 应用包括将集成电路器件置于复位状态，直到电源达到功能电压电平。

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