Invention Grant
- Patent Title: Multi-layer structures and process for fabricating semiconductor devices
- Patent Title (中): 用于制造半导体器件的多层结构和工艺
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Application No.: US13416813Application Date: 2012-03-09
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Publication No.: US08652887B2Publication Date: 2014-02-18
- Inventor: Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
- Applicant: Bich-Yen Nguyen , Carlos Mazure , Richard Ferrant
- Applicant Address: FR Bernin
- Assignee: Soitec
- Current Assignee: Soitec
- Current Assignee Address: FR Bernin
- Agency: Winston & Strawn LLP
- Priority: EP11290124 20110311
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/84

Abstract:
The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing.
Public/Granted literature
- US20120231606A1 MULTI-LAYER STRUCTURES AND PROCESS FOR FABRICATING SEMICONDUCTOR DEVICES Public/Granted day:2012-09-13
Information query
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