发明授权
US08667437B2 Creating a standard cell circuit design from a programmable logic device circuit design
有权
从可编程逻辑器件电路设计创建标准单元电路设计
- 专利标题： Creating a standard cell circuit design from a programmable logic device circuit design
- 专利标题（中）： 从可编程逻辑器件电路设计创建标准单元电路设计
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申请号： US12049676申请日： 2008-03-17
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公开(公告)号： US08667437B2公开(公告)日： 2014-03-04
- 发明人: Salil Ravindra Raje , Dinesh D. Gaitonde
- 申请人： Salil Ravindra Raje , Dinesh D. Gaitonde
- 申请人地址： US CA San Jose
- 专利权人： Xilinx, Inc.
- 当前专利权人： Xilinx, Inc.
- 当前专利权人地址： US CA San Jose
- 代理商 Kevin T. Cuenot; LeRoy D. Maunu; Lois D. Cartier
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A computer-implemented method of converting a circuit design for a programmable logic device (PLD) to a standard cell circuit design can include unmapping a PLD circuit design to a gate level netlist, mapping logic gates of the netlist to functionally equivalent standard cells, and including the standard cells within the standard cell circuit design. Design constraints for the standard cell circuit design can be automatically generated. The design constraints for the standard cell circuit design can be output.
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