发明授权
- 专利标题: System for optimizing number of dies produced on a wafer
- 专利标题(中): 用于优化在晶片上生产的模具数量的系统
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申请号: US13723207申请日: 2012-12-21
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公开(公告)号: US08671381B1公开(公告)日: 2014-03-11
- 发明人: Peidong Wang , Zhijun Chen , Zhihong Cheng , Li Ying
- 申请人: Peidong Wang , Zhijun Chen , Zhihong Cheng , Li Ying
- 申请人地址: US TX Austin
- 专利权人: Freescale Semiconductor, Inc.
- 当前专利权人: Freescale Semiconductor, Inc.
- 当前专利权人地址: US TX Austin
- 代理商 Charles Bergere
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A system for optimizing the number of dies that can be fabricated on a wafer uses a die number optimization (DNO) routine to determine a maximum number of dies for a target die area (TDA), and generate an initial result list of die shapes that have the maximum number of dies for the TDA. Optionally, a die size optimization (DSO) routine can be executed to determine a list of die shapes having a maximum die area corresponding to the maximum number of dies, a first list of optimized die shapes having a maximum area utilization (AU) for a decreased TDA, and/or a second list of optimized die shapes having a minimum AU for an increased TDA. A candidate list (CL) of the various die shapes can be generated, and entries from the CL automatically selected and/or displayed to indicate proposed wafer layouts.
公开/授权文献
- US20140096103A1 SYSTEM FOR OPTIMIZING NUMBER OF DIES PRODUCED ON A WAFER 公开/授权日:2014-04-03