公开(公告)号：US20140096103A1

公开(公告)日：2014-04-03

申请号：US13723207

申请日：2012-12-21

申请人： Peidong Wang ,  Zhijun Chen ,  Zhihong Cheng ,  Li Ying

发明人： Peidong Wang ,  Zhijun Chen ,  Zhihong Cheng ,  Li Ying

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G03F7/70433 ,  G06F2217/12 ,  Y02P90/265

摘要： A system for optimizing the number of dies that can be fabricated on a wafer uses a die number optimization (DNO) routine to determine a maximum number of dies for a target die area (TDA), and generate an initial result list of die shapes that have the maximum number of dies for the TDA. Optionally, a die size optimization (DSO) routine can be executed to determine a list of die shapes having a maximum die area corresponding to the maximum number of dies, a first list of optimized die shapes having a maximum area utilization (AU) for a decreased TDA, and/or a second list of optimized die shapes having a minimum AU for an increased TDA. A candidate list (CL) of the various die shapes can be generated, and entries from the CL automatically selected and/or displayed to indicate proposed wafer layouts.

摘要翻译： 用于优化晶片上可制造的管芯数量的系统使用管芯数量优化（DNO）程序来确定目标管芯区域（TDA）的最大数量的管芯，并且生成模具形状的初始结果列表，其中， 具有TDA的最大数量的模具。 可选地，可以执行管芯尺寸优化（DSO）程序以确定具有与最大数量的管芯相对应的最大管芯面积的管芯形状的列表，具有最大面积利用率（AU）的优化管芯形状的第一列表， 和/或用于增加的TDA具有最小AU的优化模具形状的第二列表。 可以生成各种模具形状的候选列表（CL），并且自动选择和/或显示来自CL的条目以指示所提出的晶片布局。

公开(公告)号：US08671381B1

公开(公告)日：2014-03-11

申请号：US13723207

申请日：2012-12-21

申请人： Peidong Wang ,  Zhijun Chen ,  Zhihong Cheng ,  Li Ying

发明人： Peidong Wang ,  Zhijun Chen ,  Zhihong Cheng ,  Li Ying

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G03F7/70433 ,  G06F2217/12 ,  Y02P90/265

摘要： A system for optimizing the number of dies that can be fabricated on a wafer uses a die number optimization (DNO) routine to determine a maximum number of dies for a target die area (TDA), and generate an initial result list of die shapes that have the maximum number of dies for the TDA. Optionally, a die size optimization (DSO) routine can be executed to determine a list of die shapes having a maximum die area corresponding to the maximum number of dies, a first list of optimized die shapes having a maximum area utilization (AU) for a decreased TDA, and/or a second list of optimized die shapes having a minimum AU for an increased TDA. A candidate list (CL) of the various die shapes can be generated, and entries from the CL automatically selected and/or displayed to indicate proposed wafer layouts.

摘要翻译： 用于优化晶片上可制造的管芯数量的系统使用管芯数量优化（DNO）程序来确定目标管芯区域（TDA）的最大数量的管芯，并且生成模具形状的初始结果列表，其中， 具有TDA的最大数量的模具。 可选地，可以执行管芯尺寸优化（DSO）程序以确定具有与最大数量的管芯相对应的最大管芯面积的管芯形状的列表，具有最大面积利用率（AU）的优化管芯形状的第一列表， 和/或用于增加的TDA具有最小AU的优化模具形状的第二列表。 可以生成各种模具形状的候选列表（CL），并且自动选择和/或显示来自CL的条目以指示所提出的晶片布局。

公开(公告)号：US20150084680A1

公开(公告)日：2015-03-26

申请号：US14191403

申请日：2014-02-26

申请人： Zhihong Cheng ,  Zhijun Chen ,  Huabin Du ,  Peidong Wang ,  Shayan Zhang

发明人： Zhihong Cheng ,  Zhijun Chen ,  Huabin Du ,  Peidong Wang ,  Shayan Zhang

IPC分类号： H03K17/22

CPC分类号： G11C5/14

摘要： A state retention power gated (SRPG) cell includes a retention circuit coupled to a power gated circuit. The retention circuit stores state information of the power gated circuit before a low power period is started. A gated power supply coupled to the power gated circuit and to a first end of a power supply switch supplies a gated supply voltage to the power gated circuit during a non-low power period. A local power supply coupled to the retention circuit and to a second end of the power supply switch is coupled to the gated power supply in the non-low power period, and a non-gated power supply is coupled to the local power supply via an isolation element to isolate the non-gated power supply from the local power supply during the non-low power period, and to couple the non-gated power supply to the local power supply during the low power period.

摘要翻译： 状态保持功率门控（SRPG）单元包括耦合到电源门控电路的保持电路。 保持电路在开始低功率周期之前存储电源门控电路的状态信息。 耦合到电源门控电路和电源开关的第一端的门控电源在非低功率时段期间向门控电路提供门控电源电压。 耦合到保持电路和电源开关的第二端的局部电源在非低功率时段内耦合到门控电源，并且非门控电源经由 隔离元件，以在非低功率周期期间将非门控电源与本地电源隔离，并且在低功率周期期间将非门控电源耦合到本地电源。

公开(公告)号：US08987786B1

公开(公告)日：2015-03-24

申请号：US14277804

申请日：2014-05-15

申请人： Miaolin Tan ,  Zhihong Cheng ,  Juan Fu ,  Peidong Wang ,  Yali Wang

发明人： Miaolin Tan ,  Zhihong Cheng ,  Juan Fu ,  Peidong Wang ,  Yali Wang

IPC分类号： H01L27/00 ,  H03K3/012 ,  H03K19/00 ,  H03K3/356 ,  H01L27/02 ,  G06F17/50

CPC分类号： H03K3/012 ,  G06F17/50 ,  H01L27/0207 ,  H01L27/0233 ,  H03K3/356 ,  H03K19/0008

摘要： A state retention power gated cell includes a logic cell arranged in two or more rows. The logic cell has an active layer including at least a first well and a second well disposed in first and second rows, respectively. In a normal operation mode, the first well is powered with a first bias voltage, the second well is powered with a second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered with VDD. In a standby mode, the first well preferably is powered down, the second well is powered with the second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered down.

摘要翻译： 状态保持功率选通单元包括布置成两行或多行的逻辑单元。 逻辑单元具有分别包括至少第一阱和第二阱的有源层，第一阱和第二阱分别布置在第一和第二行中。 在正常工作模式下，第一个阱由第一偏置电压供电，第二个阱由第二个偏置电压供电，第一个电源线由VDDC供电，第二个电源线由VDD供电。 在待机模式中，第一阱优选地断电，第二阱由第二偏置电压供电，第一电源线由VDDC供电，并且第二电源线断电。

公开(公告)号：US09148149B2

公开(公告)日：2015-09-29

申请号：US14176025

申请日：2014-02-07

申请人： Zhihong Cheng ,  Peidong Wang

发明人： Zhihong Cheng ,  Peidong Wang

IPC分类号： H03K3/289 ,  H03K19/094 ,  H03K3/3562

CPC分类号： H03K19/09429 ,  H03K3/35625

摘要： A latch circuit has a tri-state gate and a reverse tri-state gate that share the same complementary controls. The reverse tri-state gate locks an output of the tri-state gate when the tri-state gate is shut-off. The complementary control signals include a first undoped polysilicon strip. The output of the reverse tri-state gate may be coupled to the output of the tri-state gate via a second undoped polysilicon strip.

摘要翻译： 锁存电路具有共享相同互补控制的三态栅极和反向三态栅极。 当三态门关闭时，反向三态门锁定三态门的输出。 互补控制信号包括第一未掺杂多晶硅条。 反向三态栅极的输出可以经由第二未掺杂多晶硅条耦合到三态栅极的输出端。

公开(公告)号：US20150091626A1

公开(公告)日：2015-04-02

申请号：US14277804

申请日：2014-05-15

申请人： Miaolin Tan ,  Zhihong Cheng ,  Juan Fu ,  Peidong Wang ,  Yali Wang

发明人： Miaolin Tan ,  Zhihong Cheng ,  Juan Fu ,  Peidong Wang ,  Yali Wang

IPC分类号： H03K3/012 ,  H03K3/356 ,  H03K19/00

CPC分类号： H03K3/012 ,  G06F17/50 ,  H01L27/0207 ,  H01L27/0233 ,  H03K3/356 ,  H03K19/0008

摘要： A state retention power gated cell includes a logic cell arranged in two or more rows. The logic cell has an active layer including at least a first well and a second well disposed in first and second rows, respectively. In a normal operation mode, the first well is powered with a first bias voltage, the second well is powered with a second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered with VDD. In a standby mode, the first well preferably is powered down, the second well is powered with the second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered down.

摘要翻译： 状态保持功率选通单元包括布置成两行或多行的逻辑单元。 逻辑单元具有分别包括至少第一阱和第二阱的有源层，第一阱和第二阱分别布置在第一和第二行中。 在正常工作模式下，第一个阱由第一偏置电压供电，第二个阱由第二个偏置电压供电，第一个电源线由VDDC供电，第二个电源线由VDD供电。 在待机模式中，第一阱优选地断电，第二阱由第二偏置电压供电，第一电源线由VDDC供电，并且第二电源线断电。

公开(公告)号：US20140285236A1

公开(公告)日：2014-09-25

申请号：US14176025

申请日：2014-02-07

申请人： Zhihong Cheng ,  Peidong Wang

发明人： Zhihong Cheng ,  Peidong Wang

IPC分类号： H03K19/094

CPC分类号： H03K19/09429 ,  H03K3/35625

摘要： A latch circuit has a tri-state gate and a reverse tri-state gate that share the same complementary controls. The reverse tri-state gate locks an output of the tri-state gate when the tri-state gate is shut-off. The complementary control signals include a first undoped polysilicon strip. The output of the reverse tri-state gate may be coupled to the output of the tri-state gate via a second undoped polysilicon strip.

摘要翻译： 锁存电路具有共享相同互补控制的三态门和反向三态门。 当三态门关闭时，反向三态门锁定三态门的输出。 互补控制信号包括第一未掺杂多晶硅条。 反向三态栅极的输出可以经由第二未掺杂多晶硅条耦合到三态栅极的输出端。

公开(公告)号：US08650327B2

公开(公告)日：2014-02-11

申请号：US13604639

申请日：2012-09-06

申请人： Shixiang Nie ,  Zhijun Chen ,  Zhihong Cheng

发明人： Shixiang Nie ,  Zhijun Chen ,  Zhihong Cheng

IPC分类号： G06F3/00

CPC分类号： G06F15/7867

摘要： A processor with programmable virtual ports includes a plurality of in/out (IO) pins for transmitting and receiving data. The IO pins are grouped into a plurality of predefined ports, each of which has a physical address stored in one of a memory location of a memory map. The IO pins may be remapped to one or more virtual ports.

摘要翻译： 具有可编程虚拟端口的处理器包括用于发送和接收数据的多个输入/输出（IO）引脚。 IO引脚被分组成多个预定义端口，每个预定端口具有存储在存储器映射的存储器位置之一中的物理地址。 IO引脚可以被重新映射到一个或多个虚拟端口。

公开(公告)号：US09191021B1

公开(公告)日：2015-11-17

申请号：US14696482

申请日：2015-04-26

申请人： Zhiling Sui ,  Zhijun Chen ,  Zhihong Cheng ,  Yanping Zhang

发明人： Zhiling Sui ,  Zhijun Chen ,  Zhihong Cheng ,  Yanping Zhang

IPC分类号： H03M1/10 ,  H03M1/12 ,  H03M1/42 ,  H03M1/44

CPC分类号： H03M1/0639 ,  H03M1/0695 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/164 ,  H03M1/44

摘要： A pipelined analog-to-digital converter (ADC) that converts an analog input voltage signal Vin into a digital output value Dout. The ADC has a sequence of stages including a first calibrated stage having: (1) an ADC sub-module that receives Vin and provides an ADC sub-module digital output value based on Vin, (2) a DAC sub-module that receives the ADC sub-module digital output value and outputs a corresponding analog voltage signal VDAC, (3) a first difference module that generates an analog residual-voltage signal based on a difference between Vin and VDAC, and (4) an artificial-noise-insertion module that inserts an analog artificial-noise voltage signal into the residual voltage signal to generate an analog combined voltage signal. The analog combined voltage signal is used to calibrate the first calibrated stage. The artificial-noise-insertion module generates the polarity of the artificial-noise voltage signal based on the polarity of the corresponding residual voltage signal.

摘要翻译： 用于将模拟输入电压信号Vin转换为数字输出值Dout的流水线模数转换器（ADC）。 ADC具有一系列级，包括第一校准级，其具有：（1）ADC子模块，其接收Vin并基于Vin提供ADC子模块数字输出值，（2）DAC子模块，其接收 ADC子模块数字输出值，并输出相应的模拟电压信号VDAC，（3）基于Vin和VDAC之间的差产生模拟残留电压信号的第一差分模块，（4）人造噪声插入 模块，其将模拟人造噪声电压信号插入残余电压信号中以产生模拟组合电压信号。 模拟组合电压信号用于校准第一个校准级。 人造噪声插入模块基于相应的残留电压信号的极性产生人为噪声电压信号的极性。

公开(公告)号：US20130111099A1

公开(公告)日：2013-05-02

申请号：US13604639

申请日：2012-09-06

申请人： Shixiang NIE ,  Zhijun Chen ,  Zhihong Cheng

发明人： Shixiang NIE ,  Zhijun Chen ,  Zhihong Cheng

IPC分类号： G06F13/40

CPC分类号： G06F15/7867

摘要： A processor with programmable virtual ports includes a plurality of in/out (IO) pins for transmitting and receiving data. The IO pins are grouped into a plurality of predefined ports, each of which has a physical address stored in one of a memory location of a memory map. The IO pins may be remapped to one or more virtual ports.

摘要翻译： 具有可编程虚拟端口的处理器包括用于发送和接收数据的多个输入/输出（IO）引脚。 IO引脚被分组成多个预定义端口，每个预定端口具有存储在存储器映射的存储器位置之一中的物理地址。 IO引脚可以被重新映射到一个或多个虚拟端口。