Invention Grant
- Patent Title: High voltage bipolar transistor with pseudo buried layers
- Patent Title (中): 具有伪埋层的高压双极晶体管
-
Application No.: US12966078Application Date: 2010-12-13
-
Publication No.: US08674480B2Publication Date: 2014-03-18
- Inventor: Tzuyin Chiu , TungYuan Chu , Wensheng Qian , YungChieh Fan , Jun Hu , Donghua Liu , Yukun Lv
- Applicant: Tzuyin Chiu , TungYuan Chu , Wensheng Qian , YungChieh Fan , Jun Hu , Donghua Liu , Yukun Lv
- Applicant Address: CN Shanghai
- Assignee: Shanghai Hua Hong NEC Electronics Company, Limited
- Current Assignee: Shanghai Hua Hong NEC Electronics Company, Limited
- Current Assignee Address: CN Shanghai
- Agency: Sinorica, LLC
- Agent Ming Chow
- Priority: CN200910201946 20091215
- Main IPC: H01L29/66
- IPC: H01L29/66

Abstract:
A high voltage bipolar transistor with shallow trench isolation (STI) comprises the areas of a collector formed by implanting first electric type impurities into active area and connected with pseudo buried layers at two sides; Pseudo buried layers which are formed by implanting high dose first type impurity through the bottoms of STI at two sides if active area, and do not touch directly; deep contact through field oxide to contact pseudo buried layers and pick up the collectors; a base deposited on the collector by epitaxial growth and in-situ doped by second electric type impurity, in which the intrinsic base touches local collector and extrinsic base is used for base pick-up; a emitter which is a polysilicon layer deposited on the intrinsic base and doped with first electric type impurities. This invention makes the depletion region of collector/base junction from 1D (vertical) distribution to 2D (vertical and lateral) distribution. The bipolar transistor's breakdown voltages are increased by only enlarge active critical dimension (CD). This is low-cost process.
Public/Granted literature
- US20110140239A1 High Voltage Bipolar Transistor with Pseudo Buried Layers Public/Granted day:2011-06-16
Information query
IPC分类: