发明授权
US08681918B2 High jitter and frequency drift tolerant clock data recovery 有权
高抖动和频率漂移容限时钟数据恢复

High jitter and frequency drift tolerant clock data recovery
摘要:
In a method for recovery of a dock from a received digital data stream and an apparatus for recovering a clock from a received digital data stream, phase-shifted dock signals are generated from a receiver's dock. After selecting one of the phase-shifted clock signals, two other phase-shifted clock signals are determined. Depending on sample values taken at rising/falling edges of the three selected phase-shifted clock signals, counter values are increased and compared. The selection of phase-shifted clock signals and the steps of sampling the input digital data stream, comparing the values and increasing counter values, if required, are repeatedly performed until the comparison result of the counter values indicates that one of the latter determined phase-shifted clock signals strobes the received digital data stream in the center of a bit period.
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