发明授权
- 专利标题： Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance
- 专利标题（中）： 提高晶体管通道，减少浅沟槽隔离对晶体管性能的影响
-
申请号： US13221747申请日： 2011-08-30
-
公开(公告)号： US08686512B2公开(公告)日： 2014-04-01
- 发明人: Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
- 申请人： Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
- 申请人地址： US CA Mountain View
- 专利权人： Synopsys, Inc.
- 当前专利权人： Synopsys, Inc.
- 当前专利权人地址： US CA Mountain View
- 代理机构： Haynes Beffel & Wolfeld LLP
- 代理商 Warren S. Wolfeld
- 主分类号： H01L27/092
- IPC分类号： H01L27/092
摘要：
Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.