Invention Grant
- Patent Title: Combined packaged power semiconductor device
- Patent Title (中): 组合封装功率半导体器件
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Application No.: US13077720Application Date: 2011-03-31
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Publication No.: US08686546B2Publication Date: 2014-04-01
- Inventor: Yueh-Se Ho , Hamza Yilmaz , Yan Xun Xue , Jun Lu
- Applicant: Yueh-Se Ho , Hamza Yilmaz , Yan Xun Xue , Jun Lu
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha & Omega Semiconductor, Inc.
- Current Assignee: Alpha & Omega Semiconductor, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: CH Emily LLC
- Agent Chein-Hwa Tsao
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/02

Abstract:
A combined packaged power semiconductor device includes a flipped top source low-side MOSFET electrically connected to a top surface of a die paddle, a first metal interconnection plate connecting between a bottom drain of a high-side MOSFET or a top source of a flipped high-side MOSFET to a bottom drain of the low-side MOSFET, and a second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally that reduces the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.
Public/Granted literature
- US20110309454A1 COMBINED PACKAGED POWER SEMICONDUCTOR DEVICE Public/Granted day:2011-12-22
Information query
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