发明授权
- 专利标题: Low capacitance, low on resistance ESD diode
- 专利标题(中): 低电容,低导通电阻ESD二极管
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申请号: US11406694申请日: 2006-04-18
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公开(公告)号: US08704313B1公开(公告)日: 2014-04-22
- 发明人: Irfan Rahim , Cheng-Hsiung Huang
- 申请人: Irfan Rahim , Cheng-Hsiung Huang
- 申请人地址: US CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Ward & Zinna, LLC
- 主分类号: H01L29/78
- IPC分类号: H01L29/78
摘要:
An electrostatic discharge (ESD) protection structure comprising a polysilicon gate on an insulating layer on a substrate, said gate having first and second sides, a first heavily doped P-region in the substrate on the first side of the gate, a first heavily doped N-region in the substrate on the second side of the gate, and a shallow trench isolation isolating said first P-region and said first N-region from other structures in the substrate. In a first embodiment, the heavily doped regions are formed in a well having opposite conductivity to that of the substrate and a diode is formed at a PN junction between one of the heavily doped regions and the well. To minimize capacitance between the well and the substrate, the substrate is doped at a level of native doping and the well is isolated so that no other wells or heavily-doped regions are nearby in the substrate. Doping levels in the well and the dimensions of the gate are controlled to minimize on resistance (Ron) of the diode. In a second embodiment, no well is used.
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