发明授权
US08713286B2 Register files for a digital signal processor operating in an interleaved multi-threaded environment 有权
为交错多线程环境中的数字信号处理器注册文件

Register files for a digital signal processor operating in an interleaved multi-threaded environment
摘要:
A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.
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