公开(公告)号：US07676647B2

公开(公告)日：2010-03-09

申请号：US11506584

申请日：2006-08-18

Applicant: Lucian Codrescu ,  Erich Plondke ,  Taylor Simpson

Inventor： Lucian Codrescu ,  Erich Plondke ,  Taylor Simpson

IPC: G06F15/00

CPC classification number: G06F9/30101 ,  G06F9/30021 ,  G06F9/30094 ,  G06F9/3885

Abstract: A processor device is disclosed that includes a register file with a combined condition code register for scalar and vector operations. The processor device utilizes the combined condition code register for scalar and vector operations. Further, a compare operation can store resulting bits in the combined condition code register and a conditional operation can utilize the combined condition code register bits for evaluating a condition.

Abstract translation: 公开了一种处理器装置，其包括具有用于标量和矢量操作的组合条件码寄存器的寄存器文件。 处理器设备利用组合条件码寄存器进行标量和矢量操作。 此外，比较操作可以将结果位存储在组合条件码寄存器中，并且条件操作可以利用组合条件码寄存器位来评估条件。

公开(公告)号：US20080016316A1

公开(公告)日：2008-01-17

申请号：US11487284

申请日：2006-07-14

Applicant: Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  Vijaya Kumar Janjanam

Inventor： Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  Vijaya Kumar Janjanam

IPC: G06F12/00

CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F2212/684

Abstract: A method and system to indicate which page within a software-managed page table triggers an exception within a microprocessor, such as, for example, a digital signal processor, wherein a software-managed translation lookaside buffer (TLB) module receives a virtual address produced by an instruction within a Very Long Instruction Word (VLIW) packet, such as, for example, a fetch instruction, and further compares the virtual address to each stored TLB entry. If a match exists, then the TLB module outputs a corresponding mapped physical address for the instruction. Otherwise, if the VLIW packet spans two pages, where a first page is present as a TLB entry within the TLB module and the second page is missing from the stored TLB entries, an indication bit within a data field of a control register is set to identify the TLB miss exception to a software management unit. The software management unit retrieves the indication bit information from the register and further performs a page table look-up within the software-managed page table using the indication bit information in order to retrieve the missing page information. Subsequently, the missing page information is written into a new TLB entry within the TLB module for subsequent virtual address translation and execution of the packet of instructions.

Abstract translation: 一种方法和系统，用于指示软件管理的页表内的哪个页面在微处理器（例如数字信号处理器）内触发异常，其中软件管理的翻译后备缓冲器（TLB）模块接收产生的虚拟地址 通过超长指令字（VLIW）分组（例如，取指令）中的指令，并且还将虚拟地址与每个存储的TLB条目进行比较。 如果匹配存在，则TLB模块输出相应的映射物理地址。 否则，如果VLIW分组跨越两页，其中第一页作为TLB模块中的TLB条目存在，并且第二页从存储的TLB条目丢失，则将控制寄存器的数据字段内的指示位设置为 识别软件管理单元的TLB错误异常。 软件管理单元从寄存器检索指示位信息，并使用指示位信息进一步在软件管理的页表中执行页表查找，以便检索丢失页信息。 随后，丢失的页面信息被写入TLB模块中的新TLB条目，用于随后的虚拟地址转换和指令分组的执行。

公开(公告)号：US20060294341A1

公开(公告)日：2006-12-28

申请号：US11165757

申请日：2005-06-23

Applicant: Erich Plondke ,  William Anderson ,  Lucian Codrescu

Inventor： Erich Plondke ,  William Anderson ,  Lucian Codrescu

IPC: G06F12/00

CPC classification number: G06F9/4812 ,  G06F12/1027 ,  Y02D10/13 ,  Y02D10/24

Abstract: A shared translation look-aside buffer method comprises saving data stored in a first selected set of registers to a predetermined section of a thread-specific area in memory upon encountering an exception/interrupt, re-enabling exceptions and optionally interrupts, addressing a cause of the exception/interrupt while safely permitting another exception, and restoring the saved data to the first selected set of registers.

Abstract translation: 共享翻译后备缓冲方法包括：当遇到异常/中断时，将存储在第一选定寄存器组中的数据保存到存储器中线程特定区域的预定部分，重新​​启用异常和可选中断，解决原因 异常/中断，同时安全地允许另一个异常，并将保存的数据恢复到第一选定的寄存器组。

公开(公告)号：US20060242384A1

公开(公告)日：2006-10-26

申请号：US11115916

申请日：2005-04-26

Applicant: Muhammad Ahmed ,  Erich Plondke ,  Lucian Codrescu ,  William Anderson

Inventor： Muhammad Ahmed ,  Erich Plondke ,  Lucian Codrescu ,  William Anderson

IPC: G06F15/00

CPC classification number: G06F9/30149 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/3885

Abstract: A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.

Abstract translation: 公开了处理器设备，并且包括响应于存储器的存储器和定序器。 定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。 处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。 多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。 此外，多个寄存器文件中的每一个包括多个数据读取端口，并且多个寄存器堆栈中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。

公开(公告)号：US20060230253A1

公开(公告)日：2006-10-12

申请号：US11103744

申请日：2005-04-11

Applicant: Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  William Anderson ,  Taylor Simpson

Inventor： Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  William Anderson ,  Taylor Simpson

IPC: G06F15/00

CPC classification number: H04M1/72522 ,  G06F9/3012 ,  G06F9/3885 ,  H04M1/2535 ,  H04M2250/02

Abstract: A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer can support very long instruction word (VLIW) instructions and superscalar instructions. The processor device further includes a first instruction execution unit responsive to the sequencer, a second instruction execution unit responsive to the sequencer, a third instruction execution unit responsive to the sequencer, and a fourth instruction execution unit responsive to the sequencer. Further, the processor device includes a plurality of register files and each of the plurality of register files includes a plurality of registers. The plurality of register files are coupled to the sequencer and coupled to the first instruction execution unit, the second instruction execution unit, the third instruction execution unit, and the fourth instruction execution unit.

Abstract translation: 公开了处理器设备，并且包括响应于存储器的存储器和定序器。 音序器可以支持非常长的指令字（VLIW）指令和超标量指令。 处理器装置还包括响应于定序器的第一指令执行单元，响应于定序器的第二指令执行单元，响应于定序器的第三指令执行单元，以及响应于定序器的第四指令执行单元。 此外，处理器装置包括多个寄存器文件，并且多个寄存器文件中的每一个包括多个寄存器。 多个寄存器文件耦合到定序器并耦合到第一指令执行单元，第二指令执行单元，第三指令执行单元和第四指令执行单元。

公开(公告)号：US20060218559A1

公开(公告)日：2006-09-28

申请号：US11089474

申请日：2005-03-23

Applicant: Muhammad Ahmed ,  Sujat Jamil ,  Erich Plondke ,  Lucian Codrescu ,  William Anderson

Inventor： Muhammad Ahmed ,  Sujat Jamil ,  Erich Plondke ,  Lucian Codrescu ,  William Anderson

IPC: G06F9/46

CPC classification number: G06F9/3851

Abstract: Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, F, at which the multithreaded processor operates. Then, the method determines a variable thread switch timeout state for triggering the switching of the processing among the plurality of active threads. The variable thread switch timeout state varies so that each of the plurality of active threads operates at a frequency of an allocated portion of the frequency, F. The allocated portion at which the active threads operate is determined at least in part in order to optimize the operation of the multithreaded processor. The method further switches the processing from a first one of the active threads to a next one of the active threads upon the occurrence of the variable thread switch timeout state.

Abstract translation: 用于在通信（例如，CDMA）系统中处理传输的技术。 所公开的主题的一个方面包括用于在多线程处理器上处理指令的方法。 多线程处理器经由多个处理器管线处理多个线程。 该方法包括确定多线程处理器工作的工作频率F的步骤。 然后，该方法确定用于触发多个活动线程之间的处理切换的可变线程切换超时状态。 可变线程切换超时状态改变，使得多个活动线程中的每一个以所分配的频率部分F的频率运行。活动线程运行的分配部分至少部分地被确定，以便优化 操作多线程处理器。 在发生可变线程切换超时状态时，该方法还将处理从主动线程中的第一个切换到下一个活动线程。

公开(公告)号：US20060212681A1

公开(公告)日：2006-09-21

申请号：US11086475

申请日：2005-03-21

Applicant: Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  Sujat Jamil ,  William Anderson

Inventor： Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  Sujat Jamil ,  William Anderson

IPC: G06F9/30

CPC classification number: G06F9/3885 ,  G06F9/3851 ,  G06F9/3853

Abstract: An interleaved multithreading pipeline operating method comprises reading an instruction packet containing at least two instructions, steering a first instruction of the instruction packet to a first execution unit for execution and generating a first result, steering a second instruction of the instruction packet to a second execution unit for execution using the first result and generating a second result, and storing the second result.

公开(公告)号：US08281111B2

公开(公告)日：2012-10-02

申请号：US12236067

申请日：2008-09-23

Applicant: Erich Plondke ,  Lucian Codrescu ,  Remi Gurski ,  Shankar Krithivasan

Inventor： Erich Plondke ,  Lucian Codrescu ,  Remi Gurski ,  Shankar Krithivasan

IPC: G06F9/305

CPC classification number: G06F9/30018 ,  G06F7/584 ,  G06F9/30003 ,  G06F9/30032

Abstract: A system and method to execute a linear feedback-shift instruction is disclosed. In a particular embodiment the method includes executing an instruction at a processor by receiving source data and executing a bitwise logical operation on the source data and on reference data to generate intermediate data. The method further includes determining a parity value of the intermediate data, shifting the source data, and entering the parity value of the intermediate data into a data field of the shifted source data to produce resultant data.

Abstract translation: 公开了一种执行线性反馈移位指令的系统和方法。 在特定实施例中，该方法包括通过接收源数据并对源数据和参考数据执行逐位逻辑运算来执行处理器处的指令以产生中间数据。 该方法还包括确定中间数据的奇偶校验值，移位源数据，并将中间数据的奇偶校验值输入到移位的源数据的数据字段中，以产生结果数据。

公开(公告)号：US07949701B2

公开(公告)日：2011-05-24

申请号：US11498604

申请日：2006-08-02

Applicant: Lucian Codrescu ,  Erich Plondke ,  Mao Zeng

Inventor： Lucian Codrescu ,  Erich Plondke ,  Mao Zeng

IPC: G06F7/38 ,  G06F7/00 ,  G06F15/00

CPC classification number: G06F9/30043 ,  G06F9/30014 ,  G06F9/30018

Abstract: A method and system to perform shifting and rounding operations within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to shift and round data within a source register unit of a register file structure is received within a processing unit. The instruction includes a shifting bit value indicating the bit amount for a right shift operation and is subsequently executed to shift data within the source register unit to the right by an encoded bit value, calculated by subtracting a single bit from the shifting bit value contained within the instruction. A predetermined bit extension is further inserted within the vacated bit positions adjacent to the shifted data. Subsequently, an addition operation is performed on the shifted data and a unitary integer value is added to the shifted data to obtain resulting data. Finally, the resulting data is further shifted to the right by a single bit value and a predetermined bit extension is inserted within the vacated bit position to obtain the final rounded data results to be stored within a destination register unit.

Abstract translation: 描述了在执行单个指令期间在微处理器（例如数字信号处理器）内执行移位和舍入操作的方法和系统。 在处理单元内接收用于在寄存器堆结构的源寄存器单元内移位和舍入数据的指令。 该指令包括指示右移位操作的位量的移位位值，并且随后被执行以将源寄存器单元内的数据向右移位编码位值，该编码位值通过从包含在其中的移位位值中减去单个位而被计算 指示。 进一步将预定比特扩展插入与移位数据相邻的空闲比特位置。 随后，对移位的数据执行相加操作，并将一个整数值加到移位数据上，以获得结果数据。 最后，所得到的数据进一步向右移位一个位值，并且将预定的位扩展插入到空出的位位置中，以获得存储在目的地寄存器单元内的最终舍入数据结果。

公开(公告)号：US07689806B2

公开(公告)日：2010-03-30

申请号：US11487284

申请日：2006-07-14

Applicant: Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  Vijaya Kumar Janjanam

Inventor： Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  Vijaya Kumar Janjanam

IPC: G06F12/00 ,  G06F9/00

CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F2212/684

Abstract: A method and system to indicate which page within a software-managed page table triggers an exception within a microprocessor, such as, for example, a digital signal processor, wherein a software-managed translation lookaside buffer (TLB) module receives a virtual address produced by an instruction within a Very Long Instruction Word (VLIW) packet, such as, for example, a fetch instruction, and further compares the virtual address to each stored TLB entry. If a match exists, then the TLB module outputs a corresponding mapped physical address for the instruction. Otherwise, if the VLIW packet spans two pages, where a first page is present as a TLB entry within the TLB module and the second page is missing from the stored TLB entries, an indication bit within a data field of a control register is set to identify the TLB miss exception to a software management unit. The software management unit retrieves the indication bit information from the register and further performs a page table look-up within the software-managed page table using the indication bit information in order to retrieve the missing page information. Subsequently, the missing page information is written into a new TLB entry within the TLB module for subsequent virtual address translation and execution of the packet of instructions.

Abstract translation: 一种方法和系统，用于指示软件管理的页表内的哪个页面在微处理器（例如数字信号处理器）内触发异常，其中软件管理的翻译后备缓冲器（TLB）模块接收产生的虚拟地址 通过超长指令字（VLIW）分组（例如，取指令）中的指令，并且还将虚拟地址与每个存储的TLB条目进行比较。 如果匹配存在，则TLB模块输出相应的映射物理地址。 否则，如果VLIW分组跨越两页，其中第一页作为TLB模块中的TLB条目存在，并且第二页从存储的TLB条目丢失，则将控制寄存器的数据字段内的指示位设置为 识别软件管理单元的TLB错误异常。 软件管理单元从寄存器检索指示位信息，并使用指示位信息进一步在软件管理的页表中执行页表查找，以便检索丢失页信息。 随后，丢失的页面信息被写入TLB模块中的新TLB条目，用于随后的虚拟地址转换和指令分组的执行。