发明授权
- 专利标题： MOS transistors having reduced leakage well-substrate junctions
- 专利标题（中）： MOS晶体管具有减少的泄漏良好的衬底结
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申请号： US13584016申请日： 2012-08-13
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公开(公告)号： US08716097B2公开(公告)日： 2014-05-06
- 发明人: Terry James Bordelon, Jr. , Amitava Chatterjee
- 申请人： Terry James Bordelon, Jr. , Amitava Chatterjee
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 Jacqueline J. Garner; Wade J. Brady, III; Frederick J. Telecky, Jr.
- 主分类号： H01L21/20
- IPC分类号： H01L21/20 ; H01L29/93
摘要：
A Metal-Oxide Semiconductor (MOS) transistor includes a substrate having a topside semiconductor surface doped with a first dopant type having a baseline doping level. A well is formed in the semiconductor surface doped with a second doping type. The well forms a well-substrate junction having a well depletion region. A retrograde doped region is below the well-substrate junction doped with the first dopant type having a peak first dopant concentration of between five (5) and one hundred (100) times above the baseline doping level at a location of the peak first dopant concentration, wherein with zero bias across the well-substrate junction at least (>) ninety (90) % of a total dose of the retrograde doped region is below the bottom of the well depletion region. A gate structure is on the well. Source and drain regions are on opposing sides of the gate structure.