发明授权
US08722500B2 Methods for fabricating integrated circuits having gate to active and gate to gate interconnects
有权
用于制造具有栅极到栅极到栅极互连的集成电路的方法
- 专利标题： Methods for fabricating integrated circuits having gate to active and gate to gate interconnects
- 专利标题（中）： 用于制造具有栅极到栅极到栅极互连的集成电路的方法
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申请号： US13237688申请日： 2011-09-20
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公开(公告)号： US08722500B2公开(公告)日： 2014-05-13
- 发明人: Thilo Scheiper , Stefan Flachowsky , Andy Wei
- 申请人： Thilo Scheiper , Stefan Flachowsky , Andy Wei
- 申请人地址： KY Grand Cayman
- 专利权人： GlobalFoundries, Inc.
- 当前专利权人： GlobalFoundries, Inc.
- 当前专利权人地址： KY Grand Cayman
- 代理机构： Ingrassia Fisher & Lorenz, P.C.
- 主分类号： H01L21/336
- IPC分类号： H01L21/336
摘要：
Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes processing the IC in a replacement gate technology including forming dummy gates, sidewall spacers on the dummy gates, and metal silicide contacts to active areas. A fill layer is deposited and planarized to expose the dummy gates and the dummy gates are removed. A mask is formed having an opening overlying a portion of the channel region from which the dummy gate was removed and a portion of an adjacent metal silicide contact. The fill layer and a portion of the sidewall spacers exposed through the mask opening are etched to expose a portion of the adjacent metal silicide contact. A gate electrode material is deposited overlying the channel region and exposed metal silicide contact and is planarized to form a gate electrode and a gate-to-metal silicide contact interconnect.
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