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1.发明授权Methods for fabricating integrated circuits having gate to active and gate to gate interconnects 有权用于制造具有栅极到栅极到栅极互连的集成电路的方法公开(公告)号：US08722500B2
公开(公告)日：2014-05-13
申请号：US13237688
申请日：2011-09-20
申请人： Thilo Scheiper , Stefan Flachowsky , Andy Wei
发明人： Thilo Scheiper , Stefan Flachowsky , Andy Wei
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/76224 , H01L21/76895 , H01L21/76897
摘要： Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes processing the IC in a replacement gate technology including forming dummy gates, sidewall spacers on the dummy gates, and metal silicide contacts to active areas. A fill layer is deposited and planarized to expose the dummy gates and the dummy gates are removed. A mask is formed having an opening overlying a portion of the channel region from which the dummy gate was removed and a portion of an adjacent metal silicide contact. The fill layer and a portion of the sidewall spacers exposed through the mask opening are etched to expose a portion of the adjacent metal silicide contact. A gate electrode material is deposited overlying the channel region and exposed metal silicide contact and is planarized to form a gate electrode and a gate-to-metal silicide contact interconnect.
摘要翻译： 提供了用于制造包括门到活动触点的集成电路的方法。 一种方法包括在替代栅极技术中处理IC，包括在虚拟栅极上形成伪栅极，侧壁间隔物以及金属硅化物触点到有源区域。 填充层被平坦化以暴露伪栅极并且去除虚拟栅极。 形成掩模，其具有覆盖通道区域的从其去除虚拟栅极的一部分的开口和相邻的金属硅化物接触的一部分。 蚀刻填充层和暴露在掩模开口中的侧壁间隔部分，以露出相邻的金属硅化物接触部分。 沉积覆盖沟道区域和暴露的金属硅化物接触的栅电极材料，并被平坦化以形成栅电极和栅极与金属的硅化物接触互连。
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2.发明申请High-K Metal Gate Electrode Structures Formed by a Replacement Gate Approach Based on Superior Planarity of Placeholder Materials 审中-公开基于占位符材料优越平面度的替代门法形成的高K金属栅电极结构公开(公告)号：US20120196425A1
公开(公告)日：2012-08-02
申请号：US13354613
申请日：2012-01-20
申请人： Thilo Scheiper , Andy Wei , Stefan Flachowsky , Jan Hoentschel
发明人： Thilo Scheiper , Andy Wei , Stefan Flachowsky , Jan Hoentschel
IPC分类号： H01L21/762 , H01L21/28
CPC分类号： H01L29/785 , H01L21/823828 , H01L29/513 , H01L29/66545 , H01L29/66795
摘要： When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, superior process uniformity may be achieved by implementing at least one planarization process after the deposition of the placeholder material, such as the polysilicon material, and prior to actually patterning the gate electrode structures.
摘要翻译： 当基于替代栅极方法形成复杂的高k金属栅电极结构时，可以通过在诸如多晶硅材料的占位符材料的沉积之后实施至少一个平坦化工艺，并且在实际上 图案化栅电极结构。
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3.发明申请METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING GATE TO ACTIVE AND GATE TO GATE INTERCONNECTS 有权用于制造具有门到集成电路的主动和门来互连的方法公开(公告)号：US20130071977A1
公开(公告)日：2013-03-21
申请号：US13237688
申请日：2011-09-20
申请人： Thilo Scheiper , Stefan Flachowsky , Andy Wei
发明人： Thilo Scheiper , Stefan Flachowsky , Andy Wei
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L29/66545 , H01L21/76224 , H01L21/76895 , H01L21/76897
摘要： Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes processing the IC in a replacement gate technology including forming dummy gates, sidewall spacers on the dummy gates, and metal silicide contacts to active areas. A fill layer is deposited and planarized to expose the dummy gates and the dummy gates are removed. A mask is formed having an opening overlying a portion of the channel region from which the dummy gate was removed and a portion of an adjacent metal silicide contact. The fill layer and a portion of the sidewall spacers exposed through the mask opening are etched to expose a portion of the adjacent metal silicide contact. A gate electrode material is deposited overlying the channel region and exposed metal silicide contact and is planarized to form a gate electrode and a gate-to-metal silicide contact interconnect.
摘要翻译： 提供了用于制造包括门到活动触点的集成电路的方法。 一种方法包括在替代栅极技术中处理IC，包括在虚拟栅极上形成伪栅极，侧壁间隔物以及金属硅化物触点到有源区域。 填充层被平坦化以暴露伪栅极并且去除虚拟栅极。 形成掩模，其具有覆盖通道区域的从其去除虚拟栅极的一部分的开口和相邻的金属硅化物接触的一部分。 蚀刻填充层和暴露在掩模开口中的侧壁间隔部分，以露出相邻的金属硅化物接触部分。 沉积覆盖沟道区域和暴露的金属硅化物接触的栅电极材料，并被平坦化以形成栅电极和栅极与金属的硅化物接触互连。
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公开(公告)号：US08698243B2
公开(公告)日：2014-04-15
申请号：US13953349
申请日：2013-07-29
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L29/78 , H01L21/26586 , H01L29/1608 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/7848
摘要： Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.
摘要翻译： 通过引入应变诱导源极 - 漏极区域获得改进的MOSFET器件，其中栅极下方的最接近的“鼻”部分位于与器件表面不同的深度处。 在优选实施例中，间隔开的源极 - 漏极区域可以横向重叠。 这种接近度增加了应变诱导源 - 漏区对源极和漏极之间的感应沟道区域中的载流子迁移率的有利影响。 源极 - 漏极区域通过外部重新填充从栅极的两侧蚀刻的不对称空洞形成。 通过在栅极的仅一个侧壁附近形成初始腔，然后沿着预定的晶体方向蚀刻靠近栅极的两个侧壁的最后的间隔开的源极 - 漏极空腔来获得腔不对称性。 具有不同高度的不同深度和鼻部区域的完成的腔体在栅极下彼此延伸，被外源重新填充用于源极 - 漏极区域的应变诱导半导体材料。
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公开(公告)号：US20130320449A1
公开(公告)日：2013-12-05
申请号：US13482393
申请日：2012-05-29
IPC分类号： H01L21/8238 , H01L27/088 , H01L21/336
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L29/0847 , H01L29/1054 , H01L29/458 , H01L29/4925 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.
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6.发明申请METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING SUBSTRATE CONTACTS AND INTEGRATED CIRCUITS HAVING SUBSTRATE CONTACTS 有权用于制造具有基板接触的集成电路的方法和具有基板接触的集成电路公开(公告)号：US20130256901A1
公开(公告)日：2013-10-03
申请号：US13436323
申请日：2012-03-30
IPC分类号： H01L21/768 , H01L23/48 , B82Y40/00
CPC分类号： H01L21/76816 , H01L21/28518 , H01L21/743 , H01L21/76802 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts are provided. One method includes forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate. A metal silicide region is formed in the silicon substrate exposed by the first trench. A first stress-inducing layer is formed overlying the metal silicide region. A second stress-inducing layer is formed overlying the first stress-inducing layer. An ILD layer of dielectric material is formed overlying the second stress-inducing layer. A second trench is formed extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region. The second trench is filled with a conductive material.
摘要翻译： 提供了具有基板触点的集成电路的制造方法和具有基板触点的集成电路。 一种方法包括在穿过掩埋绝缘层延伸到硅衬底的SOI衬底中形成第一沟槽。 在由第一沟槽暴露的硅衬底中形成金属硅化物区域。 第一应力诱导层形成在金属硅化物区域之上。 第二应力诱导层形成在第一应力诱导层上。 介电材料的ILD层形成在第二应力诱导层上。 形成延伸穿过ILD层和第一和第二应力诱导层到金属硅化物区域的第二沟槽。 第二沟槽填充有导电材料。
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7.发明申请METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH REDUCED ELECTRICAL PARAMETER VARIATION 审中-公开用减少电气参数变化制造集成电路的方法公开(公告)号：US20130244388A1
公开(公告)日：2013-09-19
申请号：US13421604
申请日：2012-03-15
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/26586 , H01L21/823418 , H01L29/1045 , H01L29/1083 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a gate stack on a semiconductor substrate. In the method, a first halo implantation is performed on the semiconductor substrate with a first dose of dopant ions to form first halo regions therein. A second halo spacer is formed around the gate stack. Then a second halo implantation is performed on the semiconductor substrate with a second dose of dopant ions to form second halo regions therein.
摘要翻译： 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成栅叠层。 在该方法中，在第一剂量的掺杂剂离子的半导体衬底上进行第一晕圈注入，以在其中形成第一晕圈。 在栅堆叠周围形成第二晕环。 然后在第二剂量的掺杂剂离子的半导体衬底上进行第二晕圈注入，以在其中形成第二晕圈。
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8.发明授权Semiconductor device with work function adjusting layer having varied thickness in a gate width direction and methods of making same 有权具有在栅极宽度方向上具有不同厚度的功函数调节层的半导体器件及其制造方法公开(公告)号：US08508001B2
公开(公告)日：2013-08-13
申请号：US13217792
申请日：2011-08-25
CPC分类号： H01L27/1203 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L29/1037 , H01L29/1054 , H01L29/165 , H01L29/6659 , H01L29/66772 , H01L29/7834 , H01L29/78654
摘要： Disclosed herein is a semiconductor device that includes a semiconducting substrate and a work-function adjusting layer positioned at least partially in the semiconducting substrate, the work-function adjusting layer having a middle section, opposing ends and an end region located proximate each of said opposing ends and a gate electrode positioned above the work-function adjusting layer. Each of the end regions has a maximum thickness that is at least 25% greater than an average thickness of the middle section of the work-function adjusting layer.
摘要翻译： 本文公开了一种半导体器件，其包括半导体衬底和至少部分地位于半导体衬底中的功函数调整层，所述功函数调整层具有中间部分，相对端部和靠近所述相对的每一个的端部区域 端部和位于功函调整层上方的栅电极。 每个端部区域的最大厚度比工作功能调节层的中间部分的平均厚度大至少25％。
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9.发明申请COMPLEMENTARY STRESS LINER TO IMPROVE DGO/AVT DEVICES AND POLY AND DIFFUSION RESISTORS 有权补充应力衬管改善DGO / AVT器件和聚偏振电阻公开(公告)号：US20120199912A1
公开(公告)日：2012-08-09
申请号：US13023794
申请日：2011-02-09
CPC分类号： H01L28/20 , H01L29/78 , H01L29/7843
摘要： Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices.
摘要翻译： 通过使用互补应力衬垫，在长沟道半导体器件和电阻器中电子迁移率和空穴迁移率得到改善。 实施例包括在衬底上形成长沟道半导体器件，并在半导体器件上形成互补应力衬垫。 实施例包括在衬底上形成电阻器，并通过在电阻器上形成互补应力衬垫来调谐电阻器的电阻。 使用压缩应力衬垫来改善n型器件中的电子迁移率，并且使用拉伸应力衬垫来改善p型器件中的空穴迁移率。
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10.发明申请Transistor Comprising an Embedded Sigma Shaped Sequentially Formed Semiconductor Alloy 有权晶体管包括嵌入式西格玛形成的顺序形成的半导体合金公开(公告)号：US20120161204A1
公开(公告)日：2012-06-28
申请号：US13232571
申请日：2011-09-14
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/165 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： In sophisticated transistors, a specifically designed semiconductor material, such as a strain-inducing semiconductor material, may be sequentially provided in the drain region and the source region, thereby enabling a significant degree of lateral extension of the grown semiconductor materials without jeopardizing mechanical integrity of the transistor during the processing thereof. For example, semiconductor devices having different drain and source sides may be provided on the basis of sequentially provided embedded semiconductor materials.
摘要翻译： 在复杂的晶体管中，可以在漏极区域和源极区域中顺序提供诸如应变诱导半导体材料的特殊设计的半导体材料，从而使得生长的半导体材料的显着程度的横向延伸，而不会危害机械完整性 晶体管在其处理期间。 例如，可以在依次提供的嵌入式半导体材料的基础上提供具有不同漏极和源极侧的半导体器件。
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